8 bit PCI transactions on PPC

gregory.menke at gsfc.nasa.gov gregory.menke at gsfc.nasa.gov
Tue Sep 23 23:00:03 UTC 2003


I'm porting a known-working Linux driver for some local CPCI hardware
to RTEMS, targetting the MCP750.  Its mostly working, but I <think>
I'm seeing some 8 bit PCI transactions not working.  The 16 & 32 bit
transactions work, as seen by the various driver counters and log
messages, but at least some 8 bit PCI reads are not returning correct
data & I suspect some of the writes aren't working either.  There
board's memory region is decoded by several different components on
the board itself, so its possible 8 bit ops are succeeding with some
parts and not others.  I've experiemented with different PCI_COMMAND
options as well as latency values, but so far haven't found any clues.

I traced the 8 bit read/write instructions and they match how Linux
does it (and the same driver code works on Linux).  Does anyone know
of any motorla_shared bsp issues related to PCI configuration that
might be relevant?

My next step is to get the logic analyzer hooked up onto the CPCI
backplane and trace there, but I'd just as soon avoid that if



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