Regarding the Start.S for the i386ex BSP - beginner
Puro Markku
markku.puro at insta.fi
Fri Sep 5 11:57:22 UTC 2003
> -----Original Message-----
> From: Aditya [mailto:avpenu at essex.ac.uk]
> Sent: 2. syyskuuta 2003 22:22
> To: rtems-users at rtems.com
> Subject: Regarding the Start.S for the i386ex BSP - beginner
>
>
> Dear RTEMS Users,
>
> The Start.S file lacks a CS0 section for DRAM memory. Could anyone
> please tell me how to go ahead for a DRAM memory from location 0X0 to
> 0X003FFFFF.
>
> My FLASH of 512k is on UCS of 386ex so I guess I need to change the
> strat.S for flash from 0X03f80000 to 0x03ffffff.
First, do You have Intel's ApBUILDER?(apBuilder & b386ex.exe)
If not You may find it here:
apBuilder http://www.acfr.usyd.edu.au/teaching/4th-year/mech4710-uP/material/ref/intel/index.html
b386ex.exe http://www.ai.uga.edu/ftplib/microcontrollers/8051/
That will help You on i386ex peripheral initialisation.
And 386ex User's Manual
http://www.intel.com/design/intarch/manuals/272485.htm
Some important things about 386ex CS programming:
1. When reprogramming CS lines use programming sequence
MSKL, MSKH, ADL, ADH (according to Intel). Or You can disable
all CS lines (except the one You are running in, of course;)
and reprogram those CS line You use. Or You can disable CS
just before reprograming it.
2. When programming CS lines bee careful with order of UCS,CS0..CS6
programing because You may end up situation where some of You CS
overlapping or covers whole memory.
3. Normally You have to reprogram UCS in start.S after You switch
from real mode to protected mode. If You are booting via some
bootrom etc You may have switched allready in protected mode.
Thats why You may need both start_rom.S and start_ram.S.
Here's some lines from start.S
(running from flash=UCS but some CS lines allready programmed):
--8<------------------------------------------------------------------
/*
* Disable CS lines
*/
SYM(DisableCS):
SetExRegWord(CS0MSKL, 0x1C00) # Disable CS0
SetExRegWord(CS1MSKL, 0xFC00) # Disable CS1
SetExRegWord(CS2MSKL, 0xFC00) # Disable CS2
SetExRegWord(CS3MSKL, 0x3C00) # Disable CS3
SetExRegWord(CS4MSKL, 0xFC00) # Disable CS4
SetExRegWord(CS5MSKL, 0xFC00) # Disable CS5
SetExRegWord(CS6MSKL, 0x1C00) # Disable CS6
/*
* CS1: Start address is 00H.
* Region size is 512 Kbytes.
* 2 wait states.
* Chip select 1 is Enabled.
* 16 bit data bus size in memory space.
* External bus ready is Disabled.
* SMM region is accessable during SMI access and memory access.
*/
SYM(SetCS1_PRE):
SetExRegWord(CS1ADL, 0x0702) # CS1 (RAM)
SetExRegWord(CS1ADH, 0x0000)
SetExRegWord(CS1MSKH, 0x0007)
SetExRegWord(CS1MSKL, 0xFC01) # 0x00000..0x80000 = 512Kb
/*
* UCS: Address range is 0x80000H ... 0x3f80000H.
* Region size is 512 Kbytes.
* 2 wait states.
* Upper chip select is Enabled.
* 16 bit data bus size in memory space.
* External bus ready is Disabled.
* SMM region is accessable during SMI access and memory access.
*
* Reprograming sequence MSKL, MSKH, ADL, ADH, according to Intel !!
*/
SYM(SetUCS_PRE):
SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select
SetExRegWord(UCSMSKH, 0x03F7)
SetExRegWord(UCSADL , 0x0302) # 512K block 0x80000..0x3f80000
SetExRegWord(UCSADH , 0x03F8)
/******************************************************
* The GDT must be in RAM since it must be writeable,
* So, move the whole data section down.
********************************************************/
SYM(CopyData):
cld
movw $ SYM(_ram_data_offset) , di
movw $ SYM(_ram_data_segment), cx
mov cx , es
movw $ SYM(_data_size) , cx
movw $ SYM(_rom_data_segment), ax
movw $ SYM(_rom_data_offset) , si
mov ax , ds
repne
movsb
/*****************************
* Load the Global Descriptor
* Table Register
****************************/
SYM(LoadGDTR):
data32 addr32 lgdt SYM(GDTR) # location of GDT
/***************************
* Switch to Protected Mode
***************************/
SYM(SwitchToPM):
mov cr0, eax
orw $0x1, ax
mov eax, cr0
jmp SYM(FlushIQueue)
SYM(FlushIQueue):
nop
/**************************
* Flush prefetch queue,
* and load CS selector
**************************/
SYM(LoadCSselector):
ljmpl $ GDT_CODE_PTR , $ SYM(LoadSegmentRegisters)
nop
/*
* Load the segment registers
*/
SYM(LoadSegmentRegisters):
.code32
pLOAD_SEGMENT(GDT_DATA_PTR, fs)
pLOAD_SEGMENT(GDT_DATA_PTR, gs)
pLOAD_SEGMENT(GDT_DATA_PTR, ss)
pLOAD_SEGMENT(GDT_DATA_PTR, ds)
pLOAD_SEGMENT(GDT_DATA_PTR, es)
/*
* UCS: Start address is 0x3f80000H.
* Region size is 512 Kbytes.
* 2 wait states.
* Upper chip select is Enabled.
* 16 bit data bus size in memory space.
* External bus ready is Disabled.
* SMM region is accessable during SMI access and memory access.
*
* Reprograming sequence MSKL, MSKH, ADL, ADH, according to Intel !!
*/
SYM(SetUCS):
SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select
SetExRegWord(UCSMSKH, 0x0007)
SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000
SetExRegWord(UCSADH, 0x03f8)
/*
* CS1: Start address is 00H.
* Region size is 1024 Kbytes.
* 2 wait states.
* Chip select 1 is Enabled.
* 16 bit data bus size in memory space.
* External bus ready is Disabled.
* SMM region is accessable during SMI access and memory access.
*/
SYM(SetCS1):
SetExRegWord(CS1MSKL, 0xFC00) # Disable CS1 (RAM)
SetExRegWord(CS1ADL, 0x0702) # CS1 (RAM)
SetExRegWord(CS1ADH, 0x0000)
SetExRegWord(CS1MSKH, 0x00FF)
SetExRegWord(CS1MSKL, 0xFC01) # Enable CS1
/*
* Load IDTR
*/
SYM(LoadIDTR):
--8<------------------------------------------------------------------
I hope that's help
------------------------------------------------------------------------
Markku Puro markku.puro at insta.fi Sarankulmankatu 20
tel. +358 3 2659 769 FIN-33900 Tampere
INSTRUMENTOINTI OY mobile +358 40 7092 769 http://www.insta.fi
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