BSP for MIPS32 4KC

[gregory.menke at gsfc.nasa.gov]

mikeci at acm.org writes:
 > > Ivica,
 > >
 > > I am about to start a BSP for the AMD Au1500 which is MIPS32
 > > and I wonder if you have any specific details on the context
 > > and interrupt handling changes.  If not, what makes you feel this
 > > will be the case?
 > >
 > > Thanks,
 > > Michael
 > >
 > Michael,
 > 
 > Take look in $RTEMS_HOME/cpukit/score/cpu/mips. There you have cpu.c and
 > cpu_asm.S. Edit cpu_asm.S and search for function _ISR_Handler. You will
 > see that this function returns with:
 > 
 > 	j         k1
 > 	rfe
 >         NOP
 > 
 >        .set    reorder
 > ENDFRAME(_ISR_Handler)
 > 
 > This is incorrect for MIP32. rfe instruction is reserved for R3000 and not
 > for MIP32.

Could you please define what MIPS32 is, very explicitely?  By that I
mean what register width, what cpu family, etc...  

I still don't know what MIPS32 is other than as a #define!  If its
R4000 with 32 bit registers, that should be supported right now via
_mips3.

The j k1, rfe formulation is for R3000, R4000 has its own protocol-
which is already supported by the cpukit (context switches, etc..).
At present the R4000 context employs 64 bit registers, but the MIPS
bsp's are all 32 bits, so I think at present, all MIPS support could
be shifted to that.

Gregm