BSP for MIPS32 4KC

Joel Sherrill joel.sherrill at
Wed Sep 10 17:45:37 UTC 2003

mikeci at wrote:

> Hi!
> Here are the CPU_FLAGS which work for me:
> CPU_CFLAGS = -O0 -G0 -EL -msoft-float -mips32 -Wl,-r,-EL
> MIPS32 is 32 bit arhitecture, so all registers are 32 bit. So code looks
> something like this (example):
> unsigned32 _CPU_ISR_Get_level( void )
> {
>   unsigned int sr;
>   mips_get_sr(sr);
>   //printf("current sr=%08X, ",sr);
> #if (__mips == 3) || (__mips == 32)
> /* IE bit and shift down hardware ints into bits 1 thru 6 */
>   sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
> #elif __mips == 1
> /* IEC bit and shift down hardware ints into bits 1 thru 6 */
>   sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
> #else
> #error "CPU ISR level: unknown MIPS level for SR handling"
> #endif
>   //printf("intlevel=%02X\n",sr);
>   return sr;
> }
> This way you can generaly support MIPS32, and in the same time support
> other MIPS arhitectures.
> I agree that we can discuss this concept in more details, and that it is
> not possible to support each and every MIPS CPU.

The mips port tries to do everything with instruction level
architecture definitions.  The other ports are often not this
lucky and end up following the rule of thumb that if it can
be determined using gcc CPU model cpp predefines, then it
can go in score/cpu.  If it is CPU model dependent beyond
that gcc is aware of, then it has to go into libcpu or libbsp.

If this turns out to be the case, then score/cpu ends up
relying on routines which are assumed to be provided by
libcpu.  For example, the interrupt installation varies on
i960 models so a few routines normally in score/cpu are in

Another trick is to write code which has conditionals on
mips features not mips isa levels.  Then let something
(libcpu/mips's or a .h file) turn on and off
feature flags based upon the ISA level and/or CPU model

The code above is currently ISA level but the complex
conditional code be used to define HAS_SR_STYLE_XXX or

There are multiple ways to solve a problem and sometimes
you have to move the code to a place where more specific
CPU model information is available.  That option is

I hope we can find a solution that supports all MIPS
variants.  These MIPS variations make the choices
very ugly though.

> Regards
> Ivica

Joel Sherrill, Ph.D.             Director of Research & Development
joel at                 On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
Support Available                (256) 722-9985

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