mips exception handling - help needed
corsepiu at faw.uni-ulm.de
Mon Jan 12 11:11:02 UTC 2004
On Mon, 2004-01-12 at 10:54, durai wrote:
> Ralf Corsepius wrote
> > Instructions? Do you mean asm-instructions?
> > If the compiler emits them, you probably are not using the correct
> > compiler flags, or have tripped a bug in the compiler, if asm-code
> > contains them, you need to re-write the offending code rsp. find out
> > which #defines to use to disable the offending code.
> These are valid mips instructions (lwl,lwr,swl,swr which are unaligned
> load/store instructions), due to some reasons , our processor doesnt
> implement them.
I am not familiar with the mips to the extend that would be required to
comment in detail, but this very much sounds like using incorrect
Which CPU exactly is it? Some mips folks then probably will be able to
comment further on this.
> But these instructions will be generated by the gcc, because it expects
> these instructions should be available in the cpu. (mostly you will find
> these instructions are emitted in memcpy function).
Again, this sounds either like using incorrect compiler flags (in most
cases -m... or -march=... or -mcpu=... flags), bug in gcc or similar.
> Whenever a mips cpu encounters such an unimplemented instruction, it will
> throw an RI (Reserved Instruction) exception, which should be emulated in
> the exception handler.
Agreed, but if the compiler generates an incorrect instruction, that
qualifies as a bug, which should be fixed, somewhere - It simply should
not happen ;)
> Durai wrote
> >How can I implement that handler in RTEMS? to be more precise, I wanted to
> >know how to access the processor registers inside my exception handler,
> >i wanted to know whether the processor registers will be saved before
> > calling my exception handler.
> Sorry I have posted my above question before looking at the code fully.
> I have found that all registers are stored in a CPU_Interrupt_frame
> structure and available in the "a1" register ("a0" register contains the
> interrupt vector). But I am wondering why CPU_Interrupt_frame is not passed
> as a explicit parameter to the rtems_isr_entry function (like pt_regs
> structure is passed as a parameter to the Interrupt handler).
Sorry, I can't comment on this.
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