interrupt handling on task scheduling

[Jay Monkman]

On Mon, Jul 19, 2004 at 07:11:51PM +0200, Francesco Poletti wrote:
> Hi Joel,
> thanks for the first answer...Sorry to bother you again...
> 
> We discovered that for the arm boards the function
>  _CPU_ISR_Disable(level);
>  _CPU_ISR_Enable(level);
> Doesn't change the previous state of the interrupt instead the

I'm not sure what you mean here. _CPU_ISR_Disable() sets the I and F
bits in the CPSR, and _CPU_ISR_Enable() restores them.

> _CPU_ISR_Set_level(); When is invoked it enables all the interrupt.

I just looked at this macro, and it's wrong. It always clears the I
and F bits, enabling interrupts, regardless of the value for
new_level. The macro should be:

#define _CPU_ISR_Set_level( new_level )         \
  {                                             \
    int reg = 0; /* to avoid warning */         \
    asm volatile ("MRS %0, cpsr \n"            \
                  "BIC  %0, %0, #0xc0 \n"       \
                  "ORR  %0, %0, %2 \n"          \
                  "MSR  cpsr_c, %0 \n"          \
                  : "=r" (reg)                  \
                  : "0" (reg), "r" (new_level); \
  }

And here's a patch:

Index: cpukit/score/cpu/arm/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/arm/rtems/score/cpu.h      (revision 77)
+++ cpukit/score/cpu/arm/rtems/score/cpu.h      (working copy)
@@ -572,7 +572,7 @@
                   "ORR  %0, %0, %2 \n"          \
                   "MSR  cpsr_c, %0 \n"          \
                   : "=r" (reg)                  \
-                  : "r" (reg), "0" (reg));      \
+                  : "0" (reg), "r" (new_level); \
   }

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