The maximum length of time interrupts are disabled

Fabrizio Sebastiani sebastiani at
Mon Mar 8 08:07:22 UTC 2004

Hi all,
	I have a question a general arch-indipendent question (Im using sparc-rtems 4.0.0 for ERC32)
about the maximum length of time interrupts are disabled, regarding invocation of rtems_interrupt_{disable,enable} routines.
	My question is how can I be sure that one critical section never miss an interrupt?
	Suppose to have such a tipical code:

rtems_isr_level il;

// ... critical section ....

	Its clear to me that critical section have to perform the minimum actions in order to be "fast";
	Suppose that an interrupt comes while the CPU is executing the critical section.
How i can be sure that my critical section does not take too much time before 
the re-enabling of the interrupt? How i can be sure that no critical sections will
miss some interrupt that was coming inside them?
	I found some infos in the RTEMS docs:
	For example, as explained in
	says that I should have a look at the spart architecture supplement:
	In this link there is only a statement that is obscure to me and it doesnt seem to 
answer to my original question:

"RTEMS has been optimized to insure that interrupts are disabled for less than
TBD microseconds on a 15.0 Mhz ERC32 with zero wait states.
These numbers will vary based the number of wait states and processor speed present on the target board.
[NOTE:  The maximum period with interrupts disabled is hand calculated."

have someone more infos/answers?

tnks a lot ! :)

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