8254 (Re: timer resolution et al.)

Adrian Bocaniciu a.bocaniciu at computer.org
Wed Mar 10 11:59:16 UTC 2004


there was an earlier post where someone gave 8 MHz as the clock 
frequency for the 8254 timer on PC boards.

That is not correct, on all IBM PC compatible boards the clock frequency 
for the 8254 timer is the NTSC frequency 14.31818 MHz (TV quartz 
crystals were initially used for low cost reasons) divided by 12, i.e. 
the input clock is about 1 193 182 Hz, so the resolution of the 8254 
timer is slightly better than one microsecond.  Since the only timer 
connected to the 8259 interrupt controller is 16-bit, the maximum 
interrupt period or the maximum interval between a timer triggering and 
the corresponding interrupt is about 54.9 ms (corresponding to 18.2 
ticks/second in the periodic interrupt mode).

If someone wants to have microsecond resolution for the interval between 
triggering and firing a timer, increasing the frequency of the periodic 
interrupts used by RTEMS is not a solution, as too much time will be 
spent processing the tick interrupts.

On IBM PC/AT compatibles, where the additional RTC (Motorola 146818 
compatible) does exist, the best solution is to generate the periodic 
RTEMS tick interrupt with the RTC (the restriction that the number of 
ticks per second must be a power of two has normally no importance) and 
to keep the 8254 unused by RTEMS but available as a separate 
high-resolution timer, which can be programmed to fire after intervals 
of up to 54.9 ms with a resolution that is less than one microsecond.

Of course, on boards with Pentium-compatible processors, it is better to 
forget about the obsolete 8254 and RTC timers and use instead the much 
more convenient TSC counter and APIC timer.  On Pentium boards the 8254 
is absolutely useless and the RTC should be used only for keeping the 
absolute time while the board is powered off and the RTC keeps running 
from the Li battery.  However, to get all the advantages of the TSC and 
APIC timer, which are equivalent to the timebase and decrementer 
registers of the PowerPC processors, a redesign of the timing part of 
RTEMS would be desirable, in order to eliminate the need for periodic 
tick interrupts.  The current solution, with periodic ticks, has the 
advantage that it works on any hardware, regardless how badly designed 
it was, but it has the disadvantage that either the time resolution is 
good but a lot of processor time is wasted or the resolution is bad but 
the tick-caused overhead is low.  On good hardware, with high-resolution 
clock and alarm registers, e.g. with PowerPC or Pentium processors, it 
is better to use, instead of a periodic tick, an aperiodic timer  
interrupt  that will fire as determined by the next event from the timer 
queue.  This would allow to achieve simultaneously high resolution and 
low overhead.  On such hardware, the tick interrupt is not needed for 
maintaining the clock, as the absolute time can be read from a HW 
register (TBR on PowerPC, TSC on Pentium).

                Best regards !

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