Timing of events in an ISR

[gregory.menke at gsfc.nasa.gov]

"Joel Sherrill <joel at OARcorp.com>" <joel.sherrill at OARcorp.com> writes:
 > Mark VanderVoord wrote:
 > 
 > I would expect event send to be VERY cheap even with
 > a preemption.  You should be looking at:
 > 
 >    + ISR entry (non-nested)
 >      + event_receive (non-preemptive, task readied)
 >    + ISR exit (preemptive)
 > 
 > A MIPS has a lot of context to switch but it should be
 > on the order of low single digit microseconds to do
 > any RTEMS service.  Honestly, I would expect you to
 > have to measure it in CPU cycles.
 > 

Some time ago we measured the isr service overhead on our 12mhz MIPS
R3000 (L1 cache, no L2 cache), it took just under 100us for the full
context save, isr vectoring and return- essentially the total
interrupt service overhead.

Gregm