Development Plan Proposal for Unifying Interrupt and PCI APIs

[Eric Valette]

Joel Sherrill <joel at OARcorp.com> wrote:

>   + It's intimidating :>

No. Just think I've done my part even if the downside is that I'm 
partially responsible of the current status. I would have done it last 
year but was waiting for Till to come up with a decent proposal. 
Apparently it did not happen.

> + At first structure the unified PCI and IRQ file so they are
> like this:
> 
> ... common stuff TBD ...
> 
> #if defined(x86)
> ... All of do it x86 way ...
> #else another CPU
> ... All of do it CPU way...
> #endif

How many time should I point out that IRQ are BSP dependent while 
exception are processor dependent? On many processors (m68k, mcp8XX) you 
can hardwire some IRQ, on other the IRQ is defined by soldering some 
stuff on the extension boards, so this has to be BSP dependent even if 
most of the time it end up being only processor...

I think you can also recap the expectation (requirements) we have at 
least achieved to define last time we discussed this matter.

This includes at least :
	1) A void* handle, to pass per irq specific data
	2) A way to mask a set of interrupt while another is executing (at 
least for (ix86, ppc)),
	3) Probably interrupt sharing as PCI more ore less requires it nowadays..
	
	

-- eric