ppc405 dma - vm - cache question

[gregory.menke at gsfc.nasa.gov]

Feng, Shuchen writes:
 > 
 > >The hadrware snoop should be some mechanism provided by your ethernet
 > >controller if available.  For example, it is programmable by registers
 > >if desired for my 10/100 MHZ ethernet of the mvme5500 BSP.
 > 
 > 
 > >Did anyone implement software snoop to ensure cache coherence in RTEMS ?
 > >I thought the software snoop would impose overhead that one might as
 > >well 
 > >map the  accessed memory to be non-cachable (e.g. implemented in the
 > >RTEMS motorola_shared bsp's).  Maybe someone can verify this for me.
 > 
 > I do not know how well ethernet driver perform with non-cacheable memory.

Please ask this question more specifically.

 
 > >It seems to me that PPC405 does not use the RTEMS motorola_shared bsp,
 > >and your firmware maps the accessed memory  to be cachable.
 > 
 > I really do not have the datasheet for the RTEMS motorola_shared BSP.
 > It could be that the firmware of thoses supported board already
 > had the hardware snoop turned on.  It would be better if you can
 > find out how to turn the hardware snoop on for your board. 
 > 

The motorola_shared bsp configures the system ram such that it can be
the dma target or dma source, with a bus-mastering board on the
backplane.  No additional hardware-level configuration is necessary
unless you want the hardware to do something extra.  All PCI memory
space is configured as non-cached, which I imagine is pretty much
standard these days.  Nobody is putting system ram on the pci
backplane.

Gregm