FP register corruption on new exception processing PPC BSPs

[Till Straumann]

powerpc/shared, eth_comm, mbx8xx, mpc8260ads and
possibly other 'new exception processing' style BSPs do not
save the floating point (FP) registers across dispatching
the user ISR (for performance reasons). Nevertheless, the code
always re-enables the FPU when entering the user ISR. Hence, the ISR
can silently corrupt the FPregs if it uses the FPU. Unfortunately,
FPU usage may be the implicit result of compiler optimization
(e.g., gcc uses FPregs for copying 'long long' [integer] variables)
or the explicit result of bad coding practice.

I just filed PR#774 which makes sure the FPU is disabled across
the user ISR which means that an exception will be raised if
the ISR uses the FPU making it much easier to catch illegal FPU usage.

Note that this problem is independent of whether 'lazy FP context
switching' is used or not.

-- Till