PCI API

[Kate Feng]

"chris at chriscaudle.org" wrote:

> > I thoguht  pre assigning eight buses on each PCI is enough.   There should be
> > no need to set it to be 16.  Right ?
>
> That may be acceptable for one particular current hardware implementation, but is completely unacceptable for general use.
> Once you transition to PCI-X it is common to have one bus segment per connector so that you can run at the maximum data rate (133M transfers/s, or 266M if you use the dual rate variant).  PCI Express systems will have similar issues, because that architecture is inherently point to point and relies on switches.  The switches create multiple bus segments and look to the software like multiple PCI-PCI bridges.
> Some of the large servers I work on have 64 or more bus segments.  Those systems typically run a general purpose OS rather than a real time OS, but it seems unnecessarily limiting to design an API into the RTOS or even into the BSP which is known to be far below the architectural limitations of the bus.
>

I did have concern about limiting the number of buses, which is
why I was reluctant  to go with the alternatives either.  Eight
seems to be enough for my application, but I was not sure if it will
be enought for other larger applications and larger frame.


I still think  that  adding the PCI number into the PCI API is a
more versatile and long term solution to accomodate any form
of  bus architect or any (super large or small)  scale of application.
See more below.


Gregory Menke wrote :

>>
>>  My magic tale is another  concept.  The original proposal would limit the
>>  future applications of hot changing the PCI system configuration leaving
>> other part of PCI  devices (e.g. 1 GHZ networrk) intact while the system
>> is still running.
>
>  You are making wild assumptions here about bus architectures and
> startup sequences.
>

My magic tale is not about the startup sequence.   It's about hot
changing the system configuration.  I doubt one can
predict how hardware vendor would design the bus architecture
for their board or system, which could be subject to the constraints
of the  physical layout and size  and other considerations (e.g. performance).


On the mvme5500, PCI0 allows seven more PCI devices via the PMC
slot and PMCspan.    The PCI1 is pre occcupied by the 1GHZ network and
it has one more PMC slot (no PMCspan allowed). Imagine that one
application has  five devices on PCI0.  One day, it requires to
hot adding   two more  PCI devices while the system has
been serving  for three months.  However, the application can not
disturb any other deviceson PCI1 - at least for the prebuilt 1GHZ
network.  What is the new bus number for the two added devices
based on the original proposal  ?


Maybe I am missing some point because I did not work on
other form of PCI frames.   What is it ?  I  truly doubt one
can predict how hardware vendor would design the bus
architecture.


Regards,
Kate