How to mask IRQ

Thomas Doerfler Thomas.Doerfler at
Mon May 30 05:54:22 UTC 2005

Hello Leon,

you are right, the general SIU interrupt dispatcher will restore the SIU
mask register after the IRQ function returns. This is a general problem
with the MPC8xx Interrupt Controller, you will find this behaviour in
various operating systems. The SIU Mask Register actually belongs to the
interrupt dispatcher and not to the specific interrupt handlers.

Maybe it would be possible to introduce another "handler mask" variable,
which would be applied to the mask value written to the SIU mask
register in the dispatcher code? So the mask value would consist of the
"standard" value given in the standard table (I think) plus the value in
the mask variable (whatever operation is needed to "add" these two
masks). And there could be a well-defined API extension to set/clear
bits in this additional variable.


leonp at schrieb:
>>>Hmmm, may be I miss something.
>>>The dispatcher code I see in general looks like:
>>>void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int
>>>excNum) {
>>>register unsigned oldMask;                  /* old siu pic masks */
>>>    oldMask = ppc_cached_irq_mask;
>>>    ppc_cached_irq_mask = oldMask & SIU_IvectMask[irq];
>><== the SIU_IvectMask[irq] is what I mean as currently it mask only the
>>current interrupt but could maks others. See comment in the table
>>initialization. In fact I was wrong I my first message the mak
>>possibility is currently at SIU level via this table.  Could be also
>>done at CPM but have no more doucmentation handy...
> Well, it must be my poor english...:-)
> I want to stop to receive the IRQ5 & IRQ4 interrupts at all till some other 
> event occurs, which may be reenable them.
> This decision of masking IRQ4-5 I can take only inside the ISR of the IRQ5.
> If I mask something inside the ISR, it is erased by the mask restoration 
> immediately after my ISR function.
> If I call some IRQ handling functions, it will be considered only on the next 
> interrupt occurrence.
> Where am i wrong?

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