Altivec Context Management

[Joel Sherrill <joel@OARcorp.com>]

Hi,

Based upon GCCs implicit use of the Altivec registers, I don't think we 
have any choice but to consider the vector registers as part of the 
integer context on CPU models with Altivec.  I don't have a complete 
solution formulated in my head yet but I can see these parts already:

+ Make sure gcc has a cpp predefine triggered by -maltivec

   Adding -maltivec does result in __ALTIVEC__ being defined so that much
   is good.  This is done even in the 4.6 tools.

+ Add Altivec registers to integer context.

   Use vrsave register to avoid saving any when none are in use.  If any
   are in use, save all.  Always context switch vrsave register.

   This appears unavoidable since gcc uses the Altivec registers at its
   discretion if they are available.  I can see structure copies, loops,
   etc. surprising you with gcc getting smarter.  With C++ and Ada, there
   are probably many more opportunities to do it for you.

   Make sure vrsave register is initialized to "none in use".

   Verify that gcc uses the vrsave register or we are stuck doing all
   the registers.

+ Add Altivec multilib

   If we have extra registers which gcc is aware of, this forces our hand
   and it adds a multilib.

   Whether this should be done for 4.6 tools is up for discussion but it
   is clear that gcc 4.0.x and newer definitely will have to ship with
   Altivec multilibs for RTEMS.

+ TBD: Impact of Altivec on ISR context

   If C code can arbitrarily use the vector registers, I have a feeling
   that we may have to look at vrsave during ISR entry. :(
   Otherwise, we need to ensure the the Altivec is OFF and let ISRs trap.

I think including Altivec in the integer context is fairly 
straightforward.  It is just a matter of getting the details right 
before any code is written.

I found this article online which you might find interesting.

http://www.quadros.com/pdf/article_esd-conference_05-08-2004.pdf

Comments, thoughts, etc. appreciated.  If we decide to go forward with
this path, I hope the Altivec users will pitch in implementing the few
pieces.

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel at OARcorp.com                 On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
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