Xilinx IP core drivers for RTEMS- diff attached

[gregory.menke at gsfc.nasa.gov]

Hi,

I finally got back to some long-needed config management on the gen405
bsp.  I assembled the diffs against 4.6.99.3, the file is attached for
review.

I hesitate to just check them in as some of the changes related to
uarts, fpu and memory map are highly idiosyncratic and I don't want to
mess up other people's work.  I think a compromise patch might make the
most sense, where I set up a diff that preserves the general character
of the bsp; base addresses, etc.. but gets in the updated drivers.

Our bsp was peculiar in that the 405 units have 4 uarts and no fpu at
all, meaning, the entire toolchain has to be compiled with -msoft-float
to ensure nothing at all in newlib or above uses fp registers- the
va_args are problematic since the ppc ABI allows fpu registers to be
used when handing variable arguments.  I think it is this issue that
generally forces all PPC tasks to be floating point- its quite an
annoying architectural property.

So I'd like to propose that folks interested in the Virtex 4 gen405 bsp
family have a look at the diffs and respond with issues & changes and
hopefully I can commit something that doesn't cause too much trouble.

If folks' email systems won't pass the attachment, then please email me
and I'll resend directly.

Thanks,

Greg

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