4.6 Barrier Patch for Review

[Pavel Pisa]

On Wednesday 01 March 2006 23:08, Joel Sherrill wrote:
>  #define _ISR_Enable( _level ) \
> -        _CPU_ISR_Enable( _level )
> +  do { \
> +    _CPU_ISR_Enable( _level ); \
> +    RTEMS_COMPILER_MEMORY_BARRIER(); \
> +  } while (0)

Hello Joel,

I think, that barrier and enable order has to
follow original Till Straumann's ordering,
else there is allmost neglectable but real chance,
that GCC moves something from protected region
before _ISR_Enable() after interrupt enable
instruction, because barrier is in the fact
after it and blocking only move of the code
after whole _ISR_Enable() construct.

#define _ISR_Enable( _level ) \
do { \
   RTEMS_COMPILER_MEMORY_BARRIER(); \
   _CPU_ISR_Enable( _level ); \
 } while (0)

Same for _ISR_Flash()

#define _ISR_Flash( _level ) \
  do { \
    RTEMS_COMPILER_MEMORY_BARRIER(); \
    _CPU_ISR_Flash( _level ); \
    RTEMS_COMPILER_MEMORY_BARRIER(); \
  } while(0)

Again fault is non-probable but possible in theoretically constructed case.
The two subsequent "calls" to RTEMS_COMPILER_MEMORY_BARRIER()
has zero cost in reality, because the first one already forces
moves of all data and they do not represent any instruction.

Best wishes

                Pavel Pisa