RTEMS i386 BSP shared IRQ code questions
brinkmann at nmsu.edu
Fri Sep 1 19:26:13 UTC 2006
I've got a DigitalLogic MSM800SEV PC104 card that uses an AMD Geode
LX800 processor. I'm having trouble programming interrupts on it
from an application program. For example, BSP_install_rtems_irq_handler
appears to be installing the handler at the CPU interrupt number,
NOT the 8259 IRQ number. However, looking at the code for the
devices (console, timer, etc.) which use this call shows they're
using the same routine and working!
I have a couple of questions:
1) Where does the code account for the mapping in hardware of 8259
hardware interrupt numbers to CPU interrupt numbers? In other words,
where are the CPU/8259 interrupt handler addresses loaded into the
lowest 1K of memory?
For example, see http://www.beyondlogic.org/interrupts/interupt.htm
which shows that 8259 IRQs 0->7 = CPU IRQs 0x8->0xF
and 8259 IRQs 8->15 = CPU IRQs 0x70 ->0x77.
2) Does anyone know of a document explaining in detail how interrupts work,
both on the CPU and the BSP level, expecially for the i86?
I've looked at both the C users and porting guides, which were
little help. In fact, the i386 BSP doesn't fully conform to the
porting guide because it doesn't implement 256 interrupt levels.
FYI, the interrupt code for the i386 BSP is in the RTEMS distribution
in the directory .../c/src/lib/libbsp/i386/shared/irq.
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