rtems_semaphore_obtain

[Thomas Doerfler (nt)]

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Hi,

Some while ago we had a thread on the rtems mailing list which might
handle your problem. We found out, that gcc takes the liberty to move
some memory accesses that should occure between the irq disable/enable
calls to a location before or after the irq disabled section. Try
looking for a keyword like "memory barrier" on the mailing list archive :-)

wkr,
Thomas.


Johan Zandin schrieb:
> Sergei Organov  writes:
> 
>>"Johan Zandin" <johan.zandin at space.se> writes:
>>
>>>       _Context_Switch( &executing->Registers, &heir->Registers );
>>>
>>>       executing = _Thread_Executing;
>>>
>>>       _ISR_Disable( level );         -----+
>>>                                           |  Region where
>>>    }                                      |  an occuring 
>>>                                           |  interrupt
>>>     _Thread_Dispatch_disable_level = 0;   |  causes problems
>>>                                           |
>>>     _ISR_Enable( level );            -----+
> 
> 
>>But how interrupt can occur when it's disabled in this region?! If
>>_ISR_Disable()/_ISR_Enable() don't work on your target, you have hard
>>trouble anyway.
> 
> 
> The HW interrupt occurs but is left pending until ISRs are enabled,
> so the ISR does not execute until somewhere within the _ISR_Enable call
> (in the first cycle when ISRs are enabled in the CPU again).
> 
> /Johan
> 
> -----------------------------------------------------------
> Johan Zandin                      Software Engineer
> Saab Space AB                     Phone: +46-31-735 41 47
> SE-405 15 Gothenburg, Sweden      Fax:   +46-31-735 40 00
> -----------------------------------------------------------
> 
> 
> _______________________________________________
> rtems-users mailing list
> rtems-users at rtems.com
> http://rtems.rtems.org/mailman/listinfo/rtems-users


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