ARM exception vector question

[gds]

For my type of arm (ARM946ES) there needs to be exception jump structure 
at the bottom of memory (address 0) to handle the exceptions (data 
aborts, irq, etc). Looking through the ARM specific rtems code I can't 
seem to find anything that defines this type of thing (see below, where 
workingEntry is located at 0). This is from a linux bsp that uses the 946es.

Do the current ARM bsp's in rtems not need this type of structure? Or 
possibly it's assumed to be setup by a bootloader? Or am I just not 
seeing something like this in rtems code?

I also looked at the contributed NDS project which uses ARM946ES and 
can't find this.

The items at resetJump: and below I do see how they are initialized in 
function _CPU_ISR_install_vector in score/cpukit/score/cpu/arm/cpu.c.

Thanks,
-gene

.global workingEntry
workingEntry:
	ldr	r15, resetJump
	ldr r15, undefinedInstructJump
	ldr r15, softwareInterrupt
	ldr r15, prefetchAbort
	ldr r15, dataAbort
	ldr r15, unknownVector
	ldr r15, normalIntr
	ldr r15, fiqIntr
resetJump:
.int contEntry
undefinedInstructJump:
.int contUndefInstr
softwareInterrupt:
.int contSWI
prefetchAbort:
.int contPrefetch
dataAbort:
.int contData
unknownVector:
.int contUnknownVector
normalIntr:
.int contIntr
fiqIntr:
.int contFiq