nios2_iss usability

Roger Dahlkvist ruppe at kth.se
Mon Apr 6 14:18:06 UTC 2009


Hi,

I get the same errors on the simulator and I really don't know what's causing this. You can run the examples (I have only tried a few) if you use the option below.when running the simulator. It will then ignore uninitialized memory reads.
--print-uninit-mem-reads=2
	
Instead of using the simulator I used the nios2_iss bsp as a starting point for a hardware system, and it work just perfectly!

//Roger


I can only compile this and have been bouncing questions
and suggestions with someone who really has NIOS hardware.

Hopefully they will pitch in and answer your questions.

--joel

Wei-Tsun Sun wrote:
> Dear Joel,
>
> I tried to built the RTEMS (CVS HEAD) with testsuites to try on the nios2_iss BSP.
> RTEMS and testsuites were built fine. However when I tried the
> nios2_iss with any of the test samples, I encountered a problem as
> follows:
>
> ---------------------------------------------------- cut ------------------------------------------------------------
> nios2-iss -f hello.exe -p nios2_iss.ptf
> Altera Nios II ISS Software Simulation Environment Version 5.0
> Copyright (C) 2005 Altera Corporation
>
> Info : Successfully read SOPC Builder PTF file 'nios2_iss.ptf'
> Info : The SOPC Builder system contains the following modules:
> Info :  Bus module 'cpu_0_instruction_master_bus'       - libavalon.so
> Info :  Bus module 'cpu_0_data_master_bus'      - libavalon.so
> Info :  Master module 'cpu_0'   - libaltera_nios2.so
> Info :  Slave module 'onchip_memory_0'  - libaltera_memory.so
> Info :          Address span: 0x0000-0x7FFFFFF (cpu_0_instruction_master_bus)
> Info :          Address span: 0x0000-0x7FFFFFF (cpu_0_data_master_bus)
> Info :  Slave module 'jtag_uart_0'      - libaltera_avalon_jtag_uart.so
> Info :          Address span: 0x8000000-0x8000007 (cpu_0_data_master_bus)
> Info :  Slave module 'timer_0'  - libaltera_avalon_timer.so
> Info :          Address span: 0x8001000-0x800101F (cpu_0_data_master_bus)
> Info :  Slave module 'timer_1'  - libaltera_avalon_timer.so
> Info :          Address span: 0x8002000-0x800201F (cpu_0_data_master_bus)
> Info : Configuring 'Nios2_system' model
> Info : PTF Setting jtag_uart_0/SYSTEM_BUILDER_INFO/Iss_Launch_Telnet="0" detected
> Info : 'jtag_uart_0' character stream will be displayed in this window
> Info : The host communication device for stdin is jtag_uart_0
> Info : The host communication device for stdout is jtag_uart_0
> Info : The host communication device for stderr is jtag_uart_0
> Info : Running 'Nios2_system' model
>
> Error! : Failed memory access in component cpu_0 - Reading data 0x0 from uninitialized memory (addr = 0x18880)
> Error! : Simulation failed in component cpu_0 at instruction 22456 (PC=0x9514 instr=0x2c000017).
>
> Info : Component cpu_0's program has terminated
> Info : Instructions executed = 22456
> Info : cpu_0 simulation return code 100272
> Info : Exiting Nios2_system model with return code 100274 (0 fatal errors, 2 errors, 0 warnings)
>
> ---------------------------------------------------- cut ------------------------------------------------------------
>
> I have also noticed the ChangeLog locaed at ./c/src/lib/libbsp/nios2/nios2_iss/ChangeLog mentioning:
>
>         * Makefile.am, console/console.c, startup/linkcmds: Now links but
>         clearly the starting stack overlaps regular memory and needs to be
>         moved
>
> Does it have something to do with the problem that I have ?
>
> Thank you for your time,
>
> Best regards,
>
> Wei-Tsun Sun
>
>
> ==================================================
> Wei-Tsun Sun
> PhD Candidate
> Department of Electrical and Computer Engineering
> University of Auckland, New Zealand
> Private Bag 92019
> 38 Princess Street
> Science Centre (Building 301, level 3, room 235)
> Auckland
> New Zealand
> Phone: +64 9 3737599 ext. 87060
> http://www.ece.auckland.ac.nz/~wsun013/
> ==================================================
>

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