RTEMS PowerPC progress.

[Nick Thomas]

> 
> another idea: the ppc405 knows different kinds of interrupts, including
> "critical interrupts". I am not really sure now which kinds of
> interrupts get blocked, when rtems_interrupt_disable() is called, so an
> idea would be that:
> - critical interrupts are NOT blocked
> - you/your hardware uses critical interrupts for certain
> peripherals/timer or other stuff.
> 
> If you would reveal more inforamtion on the hardware you are using, we
> might get more insight!
> 

Hi Thomas,

In cpu.h, I see the following for _CPU_ISR_Disable:

#if 0
#define _CPU_ISR_Disable( _isr_cookie ) \
  { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \
    _isr_cookie = 0; \
    asm volatile ( 
	"mfmsr %0" : \
	"=r" ((_isr_cookie)) : \
	"0" ((_isr_cookie)) \
    ); \
    asm volatile ( 
        "andc %1,%0,%1" : \
	"=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
	"0" ((_isr_cookie)), "1" ((_disable_mask)) \
    ); \
    asm volatile ( 
        "mtmsr %1" : \
	"=r" ((_disable_mask)) : \
	"0" ((_disable_mask)) \
    ); \
  }
#endif

#define _CPU_ISR_Disable( _isr_cookie ) \
  { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \
    _isr_cookie = 0; \
    asm volatile ( \
	"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
	"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
	"0" ((_isr_cookie)), "1" ((_disable_mask)) \
	); \
  }
#endif


Looks like one method didn't work, so it was '#if 0' out.

_PPC_MSR_DISABLE_MASK is defined as:

#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable
*/

#if (PPC_HAS_RFCI)
#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable
*/
#else
#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable
*/
#endif

#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)

PPC_HAS_RFCI is defined as 1.

I am using the IBM STB025xx Digital set top box integrated controller, with
a PowerPC 405.

Hope this helps.


Nick