Jamie Bowman jamie.bowman at steepestascent.com
Fri May 21 11:01:56 UTC 2010



I am currently using RTEMS 4.8.1 running on a LEON2 processor. I am
currently trying to implement a robust mechanism that allows the system I am
developing to fail gracefully on error conditions, namely those associated
with Traps. So far I have been able to successfully register trap handlers
via RTEMS for Single EDAC Corrections and Memory Unaligned Errors. These
have been registered via RTEMS using the code below and appear to work
reliably and robustly:


//MEMORY: Address Not Aligned

set_vector((rtems_isr_entry) traphandler_0x07, SPARC_SYNCHRONOUS_TRAP(trap),
1);                         //SYNCHRONOUS -> Trap


//EDAC: Single Correctable [AMBA Interrupt]

set_vector((rtems_isr_entry) traphandler_0x11,
SPARC_ASYNCHRONOUS_TRAP(trap), 1);                      // ASYNCHRONOUS ->





With regard to Double EDAC Errors, I have as yet to find a way of getting
the trap handler to work reliably. Again the handler for this trap was
registered via RTEMS using the same technique:


            //DATA: Access Exception (DOUBLE EDAC or BUSEX)



Within a single TASK system, I can get the above handler to trigger and work
reliably, however as soon as implement the trap handler within a more
complex system with multiple tasks, I get the following error via GRMON:


            Cannot continue, processor not in debug mode

watchpoint 0  __end + 0xe018 (0x401cfb50)



The other situation I wish to be able to deal with is a Bus Exception, which
again is supposed to trigger Traps 0x01, 0x09 or 0x2B. For the LEON2 a bus
exception is triggered via an input to the processor and is generated by
some external hardware I have developed. The Bus Exception is triggered on
an illegal register address access. Again these have been registered via
RTEMS using the code below:


//INSTRUCTION: Access Exception (EDAC/ BUSEX)

set_vector((rtems_isr_entry) traphandler_0x01, SPARC_SYNCHRONOUS_TRAP(trap),


//DATA: Store Exception (BUSEX)

set_vector((rtems_isr_entry) traphandler_0x2B, SPARC_SYNCHRONOUS_TRAP(trap),


Everything I have tried with regard to the Bus Exception results in the
following error via GRMON:


Cannot continue, processor not in debug mode

watchpoint 0  __end + 0x1727e0 (0x40334818)



Any help would be most appreciated.


Kind regards




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