Issue in blackfin toolchain

[Mike Frysinger]

On Thu, Jun 23, 2011 at 21:41, Rohan Kangralkar wrote:
> I have tried to narrow down the problem regarding the bfin-rtems4.11-*
> toolchain.  As Mike Frysinger pointed out it looks like ADI has not updated
> the changes back to the GNU toolchain.

"GNU toolchain" is too generic.  yes, we've been lagging behind on
gcc, but people are getting that up to speed.  your specific issue
here though doesnt seem to have anything to do with gcc.

> 1. untar the test.tar.gz file. ( tar -zxf test.tar.gz )
> 2. enter the test folder ( cd test )
> 3. Make sure the compiler is in your path and compile the file. (make )
> 3. load the program using bfin-rtems-4.11-gdb. (ddd --debugger
> bfin-rtems4.11-gdb hello)4. put break point in the tll_fpga.c file on line
> 291.

seems the rtems gdb is old/broken then.  mainline gdb seems to work fine for me:

$ /usr/local/src/gnu/gdb/gdb/gdb --version | head -1
GNU gdb (GDB) 7.3.50.20110619-cvs

$ /usr/local/src/gnu/gdb/gdb/gdb -q ./hello
Reading symbols from /home/vapier/downloads/test/hello...done.
(gdb) target sim
Connected to the simulator.
(gdb) load
Loading section .text, size 0x1c9c lma 0x0
Loading section .rodata, size 0x138 lma 0x1c9c
Loading section .data, size 0x428 lma 0x2dd4
Start address 0x0
Transfer rate: 69600 bits in <1 sec.
(gdb) l
layout  list    load
(gdb) list tll_fpga.c:1
1       /*
2        * File:         tll_fpga_loader.c
3        * Based on:
4        * Description:  Slave Serial Mode configuration/bootload
utility for Xilinx FPGAs
5        *
6        * Hemanth Kumar.V/Vivek Kedia Copyright 2009 MindTree LTD.
7        *
8        * Licensed under the GPL-2 or later
9        * Modified: Ashish Gupta, 20100106: Added UBOOT_FPGA_LOAD
10       */
(gdb) break tll_fpga.c:291
Breakpoint 1 at 0xbc4: file tll_fpga.c, line 291.
-mike