NIOS2 ISR Handler with shadow registers

Mon Dec 2 22:28:05 UTC 2013

I added the global definition for _Nios2_ISR_Status_interrupts_disabled (except I used NIOS2_ISR_STATUS_BITS_EIC_IL instead of INTERRUPT_DISABLE_IL_BITS - I assume it's the highest interrupt level in your BSP).  It successfully compiles but will crash on startup while spitting out the RTEMS shell hello message.  So it processes some ISRs successfully but then dies.  I'm not sure if there is more I need to do in my BSP.  I have it working with the below ISR handler but it doesn't do everything that yours did.

#include <rtems/score/percpu.h>

/*----------------------------------------------------------

*   Macro to store R1 to R15 to stack

*---------------------------------------------------------*/

.macro PUSH_R1_TO_R15

    stw   at,   8(sp)

    stw   r2,  12(sp)

    stw   r3,  16(sp)

    stw   r4,  20(sp)

    stw   r5,  24(sp)

    stw   r6,  28(sp)

   stw   r7,  32(sp)

    stw   r8,  36(sp)

    stw   r9,  40(sp)

    stw   r10, 44(sp)

    stw   r11, 48(sp)

    stw   r12, 52(sp)

    stw   r13, 56(sp)

    stw   r14, 60(sp)

    stw   r15, 64(sp)

.endm

/*----------------------------------------------------------

*   Macro to restore R1 to R15 from stack

*---------------------------------------------------------*/

.macro POP_R1_TO_R15

    ldw   at,   8(sp)

    ldw   r2,  12(sp)

    ldw   r3,  16(sp)

    ldw   r4,  20(sp)

    ldw   r5,  24(sp)

    ldw   r6,  28(sp)

    ldw   r7,  32(sp)

    ldw   r8,  36(sp)

    ldw   r9,  40(sp)

    ldw   r10, 44(sp)

    ldw   r11, 48(sp)

    ldw   r12, 52(sp)

    ldw   r13, 56(sp)

    ldw   r14, 60(sp)

    ldw   r15, 64(sp)

.endm

  .set  noat

  .set  nobreak

  .section  .text

  .extern _Per_CPU_Information

  .globl  _Nios2_ISR_Dispatch_with_shadow_non_preemptive

_Nios2_ISR_Dispatch_with_shadow_non_preemptive:

    /* Get previous stack */

    rdprs sp, sp, 0

    /* Get ISR Data */

    ldw r15, 4(et)

    ldw r4, 8(et)

    /* Increment ISR nest level and thread dispatch disable level */

    movia r9, _Per_CPU_Information

    ldw r10, PER_CPU_ISR_NEST_LEVEL(r9)

    ldw r11, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(r9)

    addi  r10, r10, 1

    addi  r11, r11, 1

    stw r10, PER_CPU_ISR_NEST_LEVEL(r9)

    stw r11, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(r9)

    /* Enable Interrupts */

    rdctl r5, status

    ori   r5, r5, NIOS2_STATUS_PIE_MSK

    wrctl status, r5

    /* Call ISR */

    callr r15

    /* Disable Interrupts */

    rdctl r5, status

    andi  r5, r5, %lo(NIOS2_STATUS_PIE_MSK_I)

    wrctl status, r5

    /* Decrement ISR nest level and thread dispatch disable level */

    movia r9, _Per_CPU_Information

    ldw r10, PER_CPU_ISR_NEST_LEVEL(r9)

    ldw r11, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(r9)

    subi  r10, r10, 1

    subi  r11, r11, 1

    stw r11, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(r9)

    stw r10, PER_CPU_ISR_NEST_LEVEL(r9)

    /* Restore Address */

    addi ea, ea, -4

check_thread_dispatch:

    /* Check Thread dispatch */

    bne r10, zero, thread_dispatch_done

    bne r11, zero, thread_dispatch_done

    ldw r11, PER_CPU_DISPATCH_NEEDED(r9)

    beq r11, zero, thread_dispatch_done

start_thread_dispatch:

    /* Save Context */

    addi r15, sp, -80

    stw sstatus, 68(r15)

    stw ea, 72(r15)

    /* Set thread dispatch helper address */

    movhi ea, %hiadj(thread_dispatch_helper)

    addi  ea, ea, %lo(thread_dispatch_helper)

    /* Update stack pointer in normal register set */

    wrprs sp, r15

thread_dispatch_done:

    eret

thread_dispatch_helper:

    /* Save volatile registers */

    stw   ra,  0(sp)

    PUSH_R1_TO_R15

    call  _Thread_Dispatch

    /* Restore volatile registers */

    ldw   ra,   0(sp)

    POP_R1_TO_R15

    /* Disable Interrupts */

    rdctl r5, status

    andi  r5, r5, %lo(NIOS2_STATUS_PIE_MSK_I)

    wrctl status, r5

    /* Restore context */

    ldw et, 68(sp)

    ldw ea, 72(sp)

    addi  sp, sp, 80

    wrctl estatus, et

    eret

> Hello Kevin,

> On 2013-11-25 22:05, Kirspel, Kevin wrote:

>> I have been trying to get RTEMS up and running with a Altera NIOS II

>> processor with external VIC and shadows registers (non preemptive

>> mode).  I see that the current head has ISR support for the NIOS

>> external interrupt controller but I think it is broken.  There is a reference to a variable called

>> ?_Nios2_ISR_Status_interrupts_disabled? but I can?t find its declaration.   It

>> doesn?t seemed to exist.

> the support for external VIC works well.  You have to provide something like this in your BSP:

> static void set_isr_status_symbols(void) {

>    __asm__ volatile (

>      ".globl _Nios2_ISR_Status_mask\n"

>      ".globl _Nios2_ISR_Status_bits\n"

>      ".globl _Nios2_ISR_Status_interrupts_disabled\n"

>      ".set _Nios2_ISR_Status_mask, "

>        __XSTRING(NIOS2_ISR_STATUS_MASK_EIC_IL) "\n"

>      ".set _Nios2_ISR_Status_bits, "

>        __XSTRING(INTERRUPT_DISABLE_IL_BITS) "\n"

>      ".set _Nios2_ISR_Status_interrupts_disabled, "

>        __XSTRING(INTERRUPT_DISABLE_IL_BITS | NIOS2_STATUS_PIE) "\n"

>    );

> }

> Our BSPs are currently not in the tree since it they are automatically generated from the design files.

> --

> Sebastian Huber, embedded brains GmbH

> Address : Dornierstr. 4, D-82178 Puchheim, Germany

> Phone   : +49 89 189 47 41-16

> Fax     : +49 89 189 47 41-09

> E-Mail  : sebastian.huber at embedded-brains.de<mailto:sebastian.huber at embedded-brains.de>

> PGP     : Public key available on request.

> Diese Nachricht ist keine gesch?ftliche Mitteilung im Sinne des EHUG.

Kevin Kirspel
Senior Research Engineer
Opti Medical
235 Hembree Park Drive
Roswell GA 30076
Tel: (770)-510-4444 ext. 81642
Direct: (770)-688-1642
Fax: (770)-510-4445

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