ARM (Thumb Mode) _CPU_Context_switch_arm
Joel Sherrill
joel.sherrill at OARcorp.com
Mon Feb 25 20:45:01 UTC 2013
On 2/25/2013 2:14 PM, Matthew J Fletcher wrote:
> Joel,
>
> _CPU_Context_Initialize in cpu.c uses a hardcoded (to 0x13, not even
> using a #define) arm_cpu_mode variable to define the cpsr.
>
> #define ARM_PSR_M_SVC 0x13
>
> from cpu.h might be a good start.
>
> Although i just noticed the changelog,... oops.
>
> 2008-04-17 Joel Sherrill <joel.sherrill at oarcorp.com>
>
> * cpu.c: Add arm_cpu_mode so ARM BSP can overrid default value for cpsr.
>
> Maybe if this was an extern and the BSP defined the variable and
> initialised it it would be easier to notice. I never thought of looking
> in cpu.c for places to modify.
>
Wow! I don't remember that change at all. It doesn't even sound like the
way I would normally solve this problem. :(
Sebastian.. do you remember this?
is there a better way to accomplish this?
>
> On 25/02/13 19:53, Joel Sherrill wrote:
>> On 2/25/2013 1:37 PM, Matthew J Fletcher wrote:
>>> Hi,
>>>
>>> I guess it my fault for not 100% copying the rtl22xx BSP into my new
>>> one, i had the cpsr register in a different state at boot_card() time
>>> than the generic ARM context switch code expects. I think that common
>>> binary blob commercial RTOS must do a cpsr read before the first
>>> context switch, rather than rely on a fixed state as i've not
>>> encountered this type of issue before.
>>>
>>>
>> Some architectures construct the entire value of the status register. Others
>> start with what the BSP had and modify it.
>>
>> The question is which bits mattered and why RTEMS missed them. Could
>> we generically know the complete set of correct bits to set?
>>
>> If so, it is definitely safer to compute the entire value of a task's
>> status register.
>>
>> --joel
>>> On 25 Feb 2013 17:40, "Joel Sherrill" <joel.sherrill at oarcorp.com
>>> <mailto:joel.sherrill at oarcorp.com>> wrote:
>>>
>>> On 2/25/2013 11:25 AM, Matthew J Fletcher wrote:
>>>> Sebastain,
>>>>
>>>> I changed the code so now with the cpsr set as expected before
>>>> main() the context switch occurs fine and we end up in Init().
>>>>
>>> Is this a generic issue that needs addressing in the RTEMS
>>> git repo? Or something you broke accidentally when making
>>> other changes?
>>>> Thanks for all your help.
>>>>
>>> A little early for a beer here but it is definitely after 5 for
>>> Sebastian. Good job Sebastian!
>>>
>>> --joel
>>>> On 25 February 2013 17:10, Matthew J Fletcher <amimjf at gmail.com
>>>> <mailto:amimjf at gmail.com>> wrote:
>>>>
>>>> Hi,
>>>>
>>>> The cpsr thats saved out to r2 is 0x800000df, but is restored
>>>> back to 0x13. Thanks for pointing out that no cpsr change
>>>> must happen, i will check how the rtl22xx_t bsp sets up the
>>>> cpsr.
>>>>
>>>>
>>>>
>>>> On 25 February 2013 16:52, Sebastian Huber
>>>> <sebastian.huber at embedded-brains.de
>>>> <mailto:sebastian.huber at embedded-brains.de>> wrote:
>>>>
>>>> On 02/25/2013 05:47 PM, Matthew J Fletcher wrote:
>>>>
>>>> Hi,
>>>>
>>>> r2 is 0x13 before the msr, so I guess new_level must
>>>> have been 0.
>>>>
>>>> On 25 Feb 2013 15:02, "Sebastian Huber"
>>>> <sebastian.huber at embedded-brains.de
>>>> <mailto:sebastian.huber at embedded-brains.de>
>>>> <mailto:sebastian.huber at embedded-brains.de
>>>> <mailto:sebastian.huber at embedded-brains.de>>> wrote:
>>>>
>>>> On 02/25/2013 03:15 PM, Matthew J Fletcher wrote:
>>>>
>>>> Sebastian,
>>>>
>>>> The _Thread_Heir->Registers are ok into the
>>>> _Context_Switch() call, sp
>>>> and lr
>>>> both sensible.
>>>>
>>>> At the 'mrs r2, cpsr' line sp is 0x40001b2c
>>>> (rubbish) and pc sensible.
>>>>
>>>> In _restore, after the 'ldmia r1, ...'
>>>> instruction the sp and lr are loaded
>>>> with the correct values from
>>>> _Thread_Heir->Registers.
>>>>
>>>> Its the 'msr cpsr, r2' messes up the sp and lr
>>>>
>>>>
>>>> Ok, if you load undefined values into the CPSR,
>>>> then a lot of things may
>>>> happen. What is the value of r2 before the msr?
>>>> It should be 0x13.
>>>>
>>>>
>>>> Ok, then maybe the mode in the BSP execution context is
>>>> wrong. During _Context_Switch() no mode change must
>>>> happen. What is the CPSR before the msr?
>>>>
>>>> --
>>>> Sebastian Huber, embedded brains GmbH
>>>>
>>>> Address : Dornierstr. 4, D-82178 Puchheim, Germany
>>>> Phone : +49 89 189 47 41-16
>>>> <tel:%2B49%2089%20189%2047%2041-16>
>>>> Fax : +49 89 189 47 41-09
>>>> <tel:%2B49%2089%20189%2047%2041-09>
>>>> E-Mail : sebastian.huber at embedded-brains.de
>>>> <mailto:sebastian.huber at embedded-brains.de>
>>>> PGP : Public key available on request.
>>>>
>>>> Diese Nachricht ist keine geschäftliche Mitteilung im
>>>> Sinne des EHUG.
>>>>
>>>>
>>>>
>>>>
>>>> --
>>>>
>>>> regards
>>>> ---
>>>> Matthew J Fletcher
>>>>
>>>>
>>>>
>>>>
>>>> --
>>>>
>>>> regards
>>>> ---
>>>> Matthew J Fletcher
>>>>
>>>
>>> --
>>> Joel Sherrill, Ph.D. Director of Research & Development
>>> joel.sherrill at OARcorp.com <mailto:joel.sherrill at OARcorp.com> On-Line Applications Research
>>> Ask me about RTEMS: a free RTOS Huntsville AL 35805
>>> Support Available (256) 722-9985
>>>
>>
>> --
>> Joel Sherrill, Ph.D. Director of Research & Development
>> joel.sherrill at OARcorp.com On-Line Applications Research
>> Ask me about RTEMS: a free RTOS Huntsville AL 35805
>> Support Available (256) 722-9985
>>
--
Joel Sherrill, Ph.D. Director of Research & Development
joel.sherrill at OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
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