SPARC Context Switch Code

[Gedare Bloom]

On Thu, Feb 6, 2014 at 7:45 AM, Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
> On 2014-02-06 13:17, Ingolf Steinbach wrote:
>>
>> 2014-02-06 Sebastian Huber <sebastian.huber at embedded-brains.de>:

>> This switch
>> could happen at arbitrary places (in the interrupted task).
>
>
> Interrupts cannot happen at arbitrary places.  Interrupts can happen when
> interrupts are enabled.
>
> The interrupt prologue and epilogue code must take care about the
> interrupted context.  This is done usually in two steps.  The first step is
> performed by the processor and the second step is some code that
> saves/restores the rest of the volatile context.  This has nothing to do
> with the _CPU_Context_switch() function.
>
Sebastian is correct. The callee-save (volatile) registers are saved
by the ISR handler in case of an interrupt. This is a separate case
from the context switch code. In case of a dispatch from an ISR, the
return path from the dispatch (that resumes the interrupted thread)
will restore the volatile registers.

I think it is safe to remove those registers from the saved context
state during a context switch.

This issue and others involving context need to be revisited however
in case thread migrations are allowed. I believe (unverified) thread
migrations in the sparc can be complex due to the register windows and
size of the architected state.

-Gedare

>
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