How much NEON state should be saved in a context switch? (xilinx zynq)

[Sebastian Huber]

On 20/01/15 20:06, Stephen Tether wrote:
>
> On 01/18/2015 10:19 PM, users-request at rtems.org wrote:
>> the rule of thumb is to save/restore the volatile registers in the 
>> context switch and to save/restore the non-volatile registers in the 
>> exception epilogue/prologue. See also _ARMV4_Exception_interrupt.
>
> I've looked at _ARMV4_Exception_interrupt. It appears to do this:
>
> 1. Changes from INT mode to SVC mode.
> 2. Saves the NEON registers D0-7 and D16-D31 on the SVC stack.
> 3. Switches back to the INT stack but remains in SVC mode.
> 4. Calls the BSP-level interrupt handlers.
> 5. Changes back to the SVC stack.
> 6. Calls _Thread_Dispatch() if a context switch is needed.
> 7. Restores D0-7 and D16-D31 from the SVC stack.
>
>
> If the heir task is different from the executing task then 
> _CPU_Context_Switch() gets called in step 6. It's there that D8-D15 
> get saved and restored using storage in the two TCBs.
>
> This looks OK if there's no context switch since the volatile 
> registers get saved to the SVC stack and then restored from the SVC 
> stack. However if there is a context switch it looks as if the saved 
> volatile register contents from the executing task are restored from 
> the SVC stack just before control is given to the heir task. The 
> context switching code doesn't seem to do anything with what's saved 
> on the SVC stack.

The context switch code changes the stack and in case a thread is 
pre-empted via an interrupt it will resume execution in the exception 
epilogue which restores the volatile registers. In 
_ARMV4_Exception_interrupt you have to consider that this code executes 
with interrupts disabled. If you want to see this in action see test 
spcontext01 and set a break point to _CPU_Context_volatile_clobber and 
_CPU_Context_validate.

-- 
Sebastian Huber, embedded brains GmbH

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