GR712RC, RTEMS, and a Tale Of The Interleaving Interrupts

[Needell, Jerry]

My apologies for the typos and a major correction, we were running at 8Mhz, not 25 Mhz so you should have much faster responses. Sorry for the confusion. Still, avoid overflows if at all possible!!
On Feb 16, 2016, at 9:25 AM, Miller, Scott A. <scott.miller at swri.org<mailto:scott.miller at swri.org>> wrote:


​We are using several of the UARTs of the GR712RC (single core running at 25 MHz) with RTEMS.  Each of the UARTs is running at 115,200 baud.  When receiving incoming packetized data on the UARTs, they do not appear to interleave.

I have a few questions that I hope can be answered easily.

- How much switching overhead should I expect from the RTEMS interrupt manager when running the processor at 25 MHz?

- How can I measure how much time is being consumed by the interrupt manager at 25 MHz?

- Does RTEMS provide a configuration setting which enables/disables interrupt nesting?

Please advise.

Thanks in advance!

Robert Klar, Scott Miller
Southwest Research Institute​

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