[Spam?] Re: RTEMS on Zynq Microzed
chrisj at rtems.org
Wed Feb 17 00:17:18 UTC 2016
On 08/02/2016 06:58, Jan Sommer wrote:
> I can confirm that compiling the BSP with BSP_ARM_A9MPCORE_PERIPHCLK set to 333MHz fixes the timing issues.
> After some digging I think I also found out the why (for the case someone else stumbles upon this):
> RTEMS registers a timer interrupt for the global timer of the Microzed's A9 processor. It uses initialization from the arm/shared-directory because the
> global timer works similar among the A9 cores.
> The ARM Cortex-A9 MPCore TRM section 4.3  states: " The global timer is clocked by PERIPHCLK.", which is reflected in the initialization.
> However in Zynq-7000 TRM from Xilinx section 8.3.1  they say: "The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)."
> That means the shared driver initialization sets the wrong frequency for the Zynq-7000 family, because Xilinx deviated from the ARM reference implementation which then breaks the computation of ticks from timespans.
> I grepped for the BSP_ARM_A9MPCORE_PERIPHCLK-variable and corresponding functions and it seems that it is only used in the timer initialization routine. Therefore it should be safe to just change the variable to the correct timer frequency without breaking other drivers which may need the actual cpu-freqency (which is still 667 MHz in the standard setup).
I provide the following in my init.c:
* Provide the peripheral clock freq.
return XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2;
Note, the XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ name may vary depending on
your version of the Xilinx tools.
This approach removes the need for special command line options to
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