GSoC2016 organisation collaboration? RTEMS on FPGA hardware running MiSoC

Hesham Almatary heshamelmatary at
Tue Mar 8 18:19:47 UTC 2016

Hi Tim,

On Tue, Mar 8, 2016 at 11:53 AM, Tim Ansell <mithro at> wrote:

> Firstly, congratulations on getting into Google Summer of Code 2016! My
> own FOSS project TimVideos, was also accepted this year and was wondering
> if we should be working closer together.
> One of the "subprojects" of TimVideos is the HDMI2USB project which aims
> to develop open source video capture hardware. We are doing this by using a
> high speed FPGA running custom firmware using MiSoC (developed by the guys
> who did the Milkymist One). This firmware embeds a soft-CPU (either a lm32
> or a or1k) to allow us to write all the non-performance critical code in C.
> At the moment we are developing code which just runs on the "bare metal"
> but as the system gains more features we are increasingly needing the
> features a "real" operating system would give us.
> One project we would love to have a student work on, is porting RTEMS to
> the MiSoC system and then recreating our current functionality on top of
> it. However, this offers some challenges for us, as we are not really RTEMS
> developers and don't really know the exact amount of work needed to do
> this. Is anyone from RTEMS interested in helping mentor this project (or
> similar projects)? Looking at what would need to be done for supporting
> RTEMS on the MiSoC system and to replicated our current functionality I've
> found the following;
>   * It looks like RTEMS already has support for both the lm32 and or1k CPU
> architectures (from looking at cpukit/score/cpu?). Is there a way to find
> out the current "state" of these ports and how far along / what
> functionality might be missing?
> I can speak of or1k. The current BSP (SoC) is generic. It runs on or1ksim,
QEMU and Atlys FPGA board (including the or1k FuseSoC, formerly orpsoc3
with or1200 core). The cpukit/score/cpu includes the shared ISA code. The
BSP/board code lies on c/src/lib/libbsp/or1k. I read that Milkymist runs on
XC6SLX45 Spartan-6 FPGA which is the same as on the Atlys board.

The generic_or1k BSP includes basic device drivers support for UART console
(I/O) and clock driver.

If you considered or1k (as an architecture), your project will most likely
be a new BSP (like generic_or1k) with more new device drivers for your SoC,
and you can get the benefits of the other RTEMS target-independent

The project seems interesting to me given that it's an open-source hardware

 * The "MilkyMist One" system (
> ran RTEMS on their gateware (which I think is where the lm32 port comes
> from?). Their new MiSoC system shares a lot of similarities but is a
> complete rewrite in their migen language. How would you go about testing
> the existing RTEMS driver code and adapting it to the new MiSoC versions?
>  * We recently launched our own open hardware (the Numato Opsis -
> but our firmware is yet to
> support many of the features avaliable on the board. The two big ones are
> the networking interface and the USB OTG interfaces. How would you go about
> using RTEMS to help accelerate enabling those features? I assume providing
> interfaces in the gateware which are similar to existing devices would make
> things easier?
> From our side, we can definitely provide support around FPGA development
> and even hardware for students to work on.
> As well, if you get any students who are interested in open hardware, FPGA
> development or video standards that aren't a good fit for an RTEMS project
> - we would appreciate telling them to check us out! Thanks for your help
> and looking forward to collaborating.
> Tim 'mithro' Ansell
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> users at

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