RISC-V RTEMS Port

[Hesham Almatary]

Hi all,

The port is 2 years old. The RISC-V ABI has changed since then, but
for RTEMS not that much since I ported to work in M-mode.

On Wed, May 3, 2017 at 8:28 AM, Joel Sherrill <joel at rtems.org> wrote:
>
>
> On Tue, May 2, 2017 at 3:59 PM, Jiri Gaisler <jiri at gaisler.se> wrote:
>>
>> On 05/02/2017 07:17 PM, Joel Sherrill wrote:
>>
>>
>>
>> On Tue, May 2, 2017 at 12:11 PM, Molock, Dwaine S. (GSFC-5820)
>> <dwaine.s.molock at nasa.gov> wrote:
>>>
>>> Hello,
>>>
>>> Is there a RTEMS port available for the RISC-V processor?
>>
>>
>> No but it would be something we would be very happy to see happen. It
>> looks like an architecture with a great future.
>>
>> How it gets done is always the question. It could be done as a user
>> submitted port or via sponsorship of core developers implementing
>> it. If sponsoring the port is an option, we can follow up offline.
>>
>> --joel
>>
>>
>> There is a port at GitHub, see:
>>
>> https://github.com/heshamelmatary/rtems-riscv
>>
>> Seems fairly complete, so it might be used as a starting point...
>>
>
> I didn't know Hesham had done any work on a RISC-V port.  I have asked
> him for status details but it looks like there is work left. I see these
> tasks:
>
> + add riscv-rtems tool target to GNU tools and RSB
That's feasible given that the RISC-V GNU tools are now upstream (few
months ago). I already have the changes for this in my local repos.

> + there is no interrupt support yet in the port
Right. The latest RISCV privileged spec defines a standard interrupt
controller, this wasn't the case when I implemented the port.

> + there was no console driver.
Hello world can work but not with a conventional UART serial driver.
Conventionally in RISC-V, programs trap to M-mode, and M-mode software
takes over how to print out characters. 2 years ago, this was
implemented by RISC-V by providing a Host-Target-Interface (HTIF).
HTIF, communicates with something called front-end server (a shared
library if running in a simulator and an ARM exe of running on
Zynq/FPGA) to do the job. The reason that there was no UART driver at
this time (it's not part of the ISA anyway). I assume there's a UART
serial device in the newly released SiFive boards though [1], which
RTEMS can be ported to run on. AFAIK, RISC-V simulators (spike and
qemu) don't provide UART devices so far.

[1] https://dev.sifive.com/dev-kits/

> + benchmark timer is a stub
Timers ABI has changed. They are part of the privileged ISA.

> + context switch looks like integer portion and no FP.
Correct

>
> I am guessing he got it to load in an SEL-4 container and run a little. It
> is definitely a good start since it puts the stubs in place to start from.
>
It actually worked on both baremetal and/or seL4 [2].

[2] http://heshamelmatary.blogspot.com.au/2015/12/rtems-port-for-risc-v-withwithout-sel4.html

> --joel
>
>>
>> Jiri.
>>
>>
>>>
>>>
>>> Thanks,
>>> Dwaine
>>>
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>>
>>
>>
>>
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>
>
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-- 
Hesham