RISC-V RTEMS Port

[Joel Sherrill]

On Tue, May 2, 2017 at 3:59 PM, Jiri Gaisler <jiri at gaisler.se> wrote:

> On 05/02/2017 07:17 PM, Joel Sherrill wrote:
>
>
>
> On Tue, May 2, 2017 at 12:11 PM, Molock, Dwaine S. (GSFC-5820) <
> dwaine.s.molock at nasa.gov> wrote:
>
>> Hello,
>>
>> Is there a RTEMS port available for the RISC-V processor?
>>
>
> No but it would be something we would be very happy to see happen. It
> looks like an architecture with a great future.
>
> How it gets done is always the question. It could be done as a user
> submitted port or via sponsorship of core developers implementing
> it. If sponsoring the port is an option, we can follow up offline.
>
> --joel
>
>
> There is a port at GitHub, see:
>
> https://github.com/heshamelmatary/rtems-riscv
>
> Seems fairly complete, so it might be used as a starting point...
>
>
I didn't know Hesham had done any work on a RISC-V port.  I have asked
him for status details but it looks like there is work left. I see these
tasks:

+ add riscv-rtems tool target to GNU tools and RSB
+ there is no interrupt support yet in the port
+ there was no console driver.
+ benchmark timer is a stub
+ context switch looks like integer portion and no FP.

I am guessing he got it to load in an SEL-4 container and run a little. It
is definitely a good start since it puts the stubs in place to start from.

--joel


> Jiri.
>
>
>
>>
>> Thanks,
>> Dwaine
>>
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>
>
>
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