RISC-V RTEMS Support

[Joel Sherrill]

On Wed, Dec 19, 2018 at 1:11 AM Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:

> Hello Dwaine,
>
> On 18/12/2018 21:30, Molock, Dwaine S. (GSFC-5820) wrote:
> > Hello Sebastian,
> >
> > Do you have the prebuilt bit files or a Git repo of the RISC-V design
> > you used on the Digilent Genesys2 development board for RTEMS
> development?
> >
> > I’m looking into having someone modifying the E310 design for the
> > Digilent Arty board to add an external memory controller to access the
> > DDR memory.
>
> sorry, the bit files were provided by our customer and they are not
> available to everyone. The bit files itself wouldn't be a problem, but
> without documentation you cannot do much with them.
>

I am not sure if this is suitable but it is open:

https://github.com/SpinalHDL/VexRiscv


>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
> _______________________________________________
> users mailing list
> users at rtems.org
> http://lists.rtems.org/mailman/listinfo/users
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/users/attachments/20181219/30e8ec9e/attachment.html>