Task sync problems related with binary semaphore and cache memories

[Arturo Perez Garcia]

RTEMS is running in the R5 processors in lockstep mode, hence it is not 
an SMP configuration.

Thanks.

El 2018-11-27 14:45, Sebastian Huber escribió:
> On 27/11/2018 13:23, Arturo Perez Garcia wrote:
>> Hi, I have been facing thread synchronization problems.
>> 
>> I was trying to synchronize two threads using a binary semaphore to 
>> protect critical parts of the code. Today I realized that the 
>> semaphore was been acquired sequentially by both threads before It was 
>> released by any of them. This behavior has been fixed when I have 
>> disabled the cache memories, either the data cache or instruction 
>> cache. Could you give me some hint about this??
>> 
>> I'm using our own BSP for the zcu102, which was generated by modifying 
>> the xilinx-zynq bsp for the RTEMS release 4.11.3. This behavior can be 
>> related to a wrong implementation of the BSP??
> 
> Please run the smplock01 and smpatomic01 on your board. I guess the
> cache snooping is not enabled.
> 
> SMP is experimental in RTEMS 4.11. I would use the RTEMS master.

-- 
Arturo Perez Garcia - arturo.perez at upm.es

Researcher
Center of Industrial Electronics
Universidad Politecnica de Madrid