RISC-V RTEMS Support

[Sebastian Huber]

Hello Dwaine,

I finished my work to add SMP support to the RISC-V architecture for 
RTEMS. It is now on par with the ARM, PowerPC and SPARC ports. I had 
only a two hart system for testing (FPGA based). It would be nice to get 
some funding to add support for high end targets such as:

https://www.sifive.com/products/hifive-unleashed/

A ready to use SoC for a low budget FPGA development board would be also 
quite nice. The SiFive evaluation SoC for the Digilent Arty board has no 
memory controller and 16KiB internal RAM are not enough to run the RTEMS 
testsuite.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

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