Zynq Ultrascale+

[mbenson at windhoverlabs.com]

Trying the other list.  Is RTEMS actually running on a Zynq Ultrascale?  The instructions I found for the Ultra96 make me think 1) either it doesn’t actually work, or 2) there are undocumented assumptions including running the A53’s in 32bit mode.

What I’m most interested in is running RTEMS on the Cortex R5 both in split and lock step mode.

Sent from my iPhone

> On Dec 8, 2019, at 13:15, Mathew Benson <mbenson at windhoverlabs.com> wrote:
> 
> My new board arrived so I'm shelving the OcPoC (Zynq 7020) to focus on the new Zynq Ultrascale+.
> 
> https://shop.trenz-electronic.de/en/TE0820-03-2AI21FA-MPSoC-Module-with-Xilinx-Zynq-UltraScale-ZU2CG-1I-2-GByte-DDR4-SDRAM-4-x-5-cm
> 
> Has anybody ported RTEMS to the Zynq Ultrascale+?  I saw that "xilinx_zynqmp" is the arm family with "xilinx_zynqmp_ultra96" BSP.  Does this actually work?  Maybe this is a dumb question, but why is the xilinx_zynqmp_ultra96 BSP built using the arm-rtems5 toolchain?  It builds a 32 bit binary.  The Zynq Ultrascale is 64 bit.  The linux kernel built by the Xilinx Petalinux toolchain results in an aarch64 kernel.  
> 
> 
> -- 
> Mathew Benson
> CEO | Chief Engineer
> Windhover Labs, LLC
> 832-640-4018
> 
> 
> www.windhoverlabs.com
> 
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