Arm Cortex-R5 RTEMS Port/BSP?
joel at rtems.org
Tue Nov 26 21:36:30 UTC 2019
On Mon, Nov 25, 2019 at 12:42 AM Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:
> On 22/11/2019 21:57, Molock, Dwaine S. (GSFC-5820) wrote:
> > Hello,
> > Is there an Arm Cortex-R5 RTEMS support and/or Port/BSP available?
> we don't have a port, but may work with a Cortex-R52 in Q1 or Q2 next year.
There is an R52 in the HPSC and a BSP should be submitted for that in the
distant future to rtems.org. There is still some work to be done. What has
is available at https://github.com/ISI-apex/rtems
Do you have a specific target board or SoC in mind?
> > I see that there are BSP’s for the Arm Cortex-R4. The R5 is a superset
> > of the R4 with enhanced error management and extended functional safety
> > features.
> One of the main features this that is supports an EL2 which makes it a
> better target for hypervisors.
> > Can a R4 BSP be executed on a R5 and/or used as the starting point for
> > creating a R5 Port and BSP?
> Sebastian Huber, embedded brains GmbH
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone : +49 89 189 47 41-16
> Fax : +49 89 189 47 41-09
> E-Mail : sebastian.huber at embedded-brains.de
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