RISC-V .align 3 - bug or feature?

[Hesham Almatary]

On Mon, 7 Sep 2020 at 11:05, Schweikhardt, Jens (TSPCE3-TL4)
<Jens.Schweikhardt at tesat.de> wrote:
>
> hello world\n
>
>
>
> I’m looking at https://git.rtems.org/rtems/tree/bsps/riscv/shared/start/start.S  which contains near the end
>
>
>
>                 /* Wait for go issued by the boot processor (mhartid == 0) */
>
>                 LADDR  t0, .Lsecondary_processor_go
>
>
>
> .Lwait_for_go_again:
>
>
>
>                 lw           t1, 0(t0)
>
>                 fence    iorw, iorw
>
>                 bnez      t1, .Lwait_for_go_again
>
>
>
>                 mv         a0, s1
>
>                 call         bsp_start_on_secondary_processor
>
>
>
> #if __riscv_xlen == 32
>
>                 .align     2
>
> #elif __riscv_xlen == 64
>
>                 .align     3                        ß---------- Interesting.
>
> #endif
>
>
>
> .Lsecondary_processor_go:
>
>
>
>                 /*
>
>                 * These are ebreak instructions, just in case we end up here executing
>
>                 * code.
>
>                 */
>
>                 .word    0x00100073
>
> #if __riscv_xlen == 64
>
>                 .word    0x00100073
>
> #endif
>
>
>
> I’ve never come across a situation where I would want alignment 3 on a 64bit CPU.
>
> Is this alignment intended? Is it the base 2 log?
>
It's 2^3 = 8. We should probably use balign instead to avoid such confusion.

>
>
> Jens Schweikhardt
>
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-- 
Hesham