Using LwIP on the STM32H7
Mr. Andrei Chichak
groups at chichak.ca
Thu Jan 28 17:33:45 UTC 2021
I’ve been trying to get ethernet on STM32F7 going using the bsd networking stack (not going that well, there is a LOT of undocumented knowledge to straighten out).
The STM32x7 ethernet controllers need their descriptors and data areas to be located on 32-byte boundaries with a combination of cache being turned off and buffering being turned off. This is a side effect of the STM32x7 DMA and data caching.
The examples that ST have for LWiP under FreeRTOS have some issues with the linker file having overlapping sections and the stack (above the ETH data areas) being left with no cache and no buffering. The space above the rx/tx buffers is also less than the stack space minimum specified in the linker file as well. Some rearranging of the ETH descriptors and data areas would be prudent. Like push them to the top of SRAM and locate the stack below.
To get this all going, they set up the MPU for two overlapping sections, one being the top 16kB of SRAM and the other the 256B that contain the ETH descriptors. I believe the MPU regions can be set in increments of 32Bytes, so setting up the cache and buffering should be do-able without affecting the stack.
In RTEMS it appears that I have to pull the data and lengths out of some mbufs (I had to look that up), and push it all into the data areas. Using LWiP, I think you do similar things, just pulling the data out of the pbuf chains.
On the STM forums is an item about how to actually get a working ETH going on ST processors. There’s all sorts of issues including Cube generating code for ST’s dev boards that has the incorrect address for the PHY chip.
Take a look at: https://community.st.com/s/question/0D50X0000BOtfhnSQB/how-to-make-ethernet-and-lwip-working-on-stm32 <https://community.st.com/s/question/0D50X0000BOtfhnSQB/how-to-make-ethernet-and-lwip-working-on-stm32>
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