RTEMS trap handling versus RISCV mtvec BASE and MODE

Schweikhardt, Jens (TSPCE3-TL4) Jens.Schweikhardt at tesat.de
Tue Jun 1 10:05:02 UTC 2021

hello world,

I'm scratching my head over what may turn out to be a glitch in
Volume 2, Privileged Spec v. 20190608 RISC-V

In particular, the way RTEMS for RISCV sets the machine trap vector
in src/rtems/bsps/riscv/shared/start/start.S with

    LADDR  t0, _RISCV_Exception_handler
    csrw   mtvec, t0

i.e. loads the 32 bit address _RISCV_Exception_handler into mtvec.
This seems to contradict the layout oft he mtvec register documented in 3.1.7 as

mtvec:   30 bits of BASE, 2 bits of MODE.

in conjunction with Table 3.5, MODE 0, "All exceptions set pc to BASE".

This would set pc to _RISCV_Exception_handler *divided by 4* and probably crash.

So either RTEMS writes the wrong value to mtvec, or the RISC-V docs should say "All exceptions set pc to BASE x 4".
Am I missing something?



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