RTEMS trap handling versus RISCV mtvec BASE and MODE
heshamelmatary at gmail.com
Tue Jun 1 11:48:02 UTC 2021
On Tue, 1 Jun 2021 at 13:37, Schweikhardt, Jens (TSPCE3-TL4)
<Jens.Schweikhardt at tesat.de> wrote:
> Hesham Almatary wrote:
> > You might be confusing taking BASE[XLEN-1:2] (see Figure 3.8) with shifting an address by 2. RTEMS aligns _RISCV_Exception_handler to 4 bytes as per the specification, so you'd always end up with an address with zeros in the least significant 2 bits. So, BASE[1:0] will always be zero. When you write that to mtvec, you'll effectively set the MODE to 0 (Direct), and BASE[XLEN-1:2] will be placed as is in mtvec.
> > I hope that clarifies things up a bit.
> Yes it does, thanks a lot. So in the end it was a notation misinterpretation.
> FIELD[x:y] means the slice of FIELD bits ranging from bit x to bit y, NOT that FIELD is x-y bits wide.
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