RTEMS Development on Zynq 7000 Board

[Pavel Pisa]

Dear Florian,

we are using Zynq 7000 as the base for our projects,
education, motion control and CAN/CAN FD development.
For Linux and RTEMS now.

We are starting RTEMS CAN/CAN FD revwrite/bring-up
project. I am actually preparing some initial
steps progress report for RTEMS devel list now.

We use U-boot to configure FPGA part and start
RTEMS on the board.

Michal Lenc has revived and tested RTEMS on Zynq
setup to proceed with tasks for Real-Time systems
programming to run tasks including final one.
The final one is the control of DC motor from another board
running RTOS over UDP. There is even TCP http server
for monitoring.

Documentation for our educational kit (based on Microzed)

  https://cw.fel.cvut.cz/wiki/courses/b35apo/en/documentation/mz_apo/start

Startup help on mine group coordination wiki prepared by Michal Lenc 

  https://gitlab.fel.cvut.cz/otrees/rtems/work-and-ideas/-/wikis/RTEMS%20Build%20for%20mzAPO%20board

Repository with our IP cores for DC and PMSM motor control,
CAN, CAN FD controllers etc.

  https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/

All designs, code manual etc are open-source.

My another studnet works on simple VHDL 5-stage pipeline
RISC-V RVapo, which is used for education in our subjects
and he managed it into state, when he can run it in parallel
by Zynq ARM cores and Linux can be used to use it as processor.

This design can be used as another example for Xilixn Zynq
FPGA design

  https://gitlab.fel.cvut.cz/b4m35pap/rvapo-vhdl

Please, try to look into materials and then we can answer
your questions. Be prepared, that time can be problem.
If I do not respond in week, send me direct reminder
and I try to provide at least short feedback.

Best wishes,

                Pavel
--
                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa at cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
    Karlovo namesti 13, 121 35, Prague 2
    university: http://control.fel.cvut.cz/
    personal:   http://cmp.felk.cvut.cz/~pisa
    social:     https://social.kernel.org/ppisa
    projects:   https://www.openhub.net/accounts/ppisa
    CAN related:http://canbus.pages.fel.cvut.cz/
    RISC-V education: https://comparch.edu.cvut.cz/
    Open Technologies Research Education and Exchange Services
    https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home


On Thursday 09 of November 2023 11:09:15 Stanislav Pankevich wrote:
> Hi Florian,
>
> Thanks for asking. I am not working on that project anymore. We definitely
> brought up RTEMS to run on ARTY with some tinkering behind it, but we could
> not open-source our setup due to lack of time. I am most certain that we
> used the xilinx_zynq_zc702 configuration as a base. Now I don't have access
> to the working code but only some memories. I am working on another Xilinx
> part now, and since the setups are in a way similar, let me share what I
> can.
>
> As already indicated in the original RTEMS thread, there are two workflows
> possible:
>
> 1) Vivado/Vitis/XSDB/GDB
>
> 1.1) Create FPGA design in Vivado, export design file.
> 1.2) Create Platform project in Vitis from the exported design file from
> step 1.1.
> 1.3) Create a SW project in Vitis based on the Platform project in step
> 1.2. 1.4) Use Vitis to Flash and Debug the software in IDE.
> 1.5) When the setup is stable, check the log panels of Vitis to understand:
> - Which TCL commands Vitis runs to configure the board and flash the
> software.
> - See the logs that those commands themselves produce to get a better
> understanding of the board startup sequence.
>
> From here on, you copy what Vitis does in the IDE to your command-line
> workflow to automate things and not be dependent on the IDE workflow (if
> you want).
>
> 1.6) Copy the TCL commands that Vitis does to TCL files on your file system
> and run the Xilinx XSDB from the command line to reproduce exactly the
> steps of what Vitis does during the IDE flash&debug workflow. The result of
> this step is that you can do 100% the same things compared to what Vitis
> does, but from your own command-line scripts. I am attaching our current
> top-level file that does the flashing but the related details of how to
> source the TCL files you should figure out yourself, following the Vitis
> logs from 1.5.
> 1.7) Once you can flash with XSDB, you can also connect to it with GDB
> because XSDB has a GDB server.
>
> *) Note that there are two ways of starting the SW: with and without the
> Xilinx First-Stage Bootloader (FSBL) run in the process. If you just Flash
> with your debugger and not boot from Flash memory, running of something
> like $VITIS_PATH/scripts/vitis/util/fsbl.tcl should be part of your scripts
> or if you include the "FSBL" checkbox in Vitis, also the fsbl binary to be
> run before you flash your image. The main point to remember the FSBL
> startup sequence has to be run either by the FSBL itself if it gets flashed
> or by a corresponding FSBL TCL script. Following the Vitis logs, you should
> notice exactly those lines.
>
> This is the workflow that we are using now and everything pretty much
> works. In 2021, my colleague skipped the steps 1.6-1.7 and implemented
> workflow #2, see below.
>
> 2) OpenOCD/GDB
>
> To enable OpenOCD, you should anyway familiarize yourself with the steps
> from 1.1-1.6. Instead of copying the Vitis logs commands to TCL files like
> in step 1, the action here is to configure OpenOCD and GDB to reproduce
> exactly those steps but using OpenOCD/GDB syntax and commands.
>
> You will likely need at least two files:
>
> - OpenOCD config file, something like arty.cfg which you will run with
> openocd, like "openocd -f arty.cfg"
> - GDB init file which you can run source when you run GDB: gdb -x
> rtems.gdb. In that GDB file you can have a function like "flash" which will
> reproduce the necessary TCL scripts commands from Vitis.
>
> A general guidance for setting up the workflow #2 can be found here but you
> will have to adapt it to your needs:
> https://devel.rtems.org/wiki/Debugging/OpenOCD/Xilinx_Zynq.
>
> In the attached Python file, you see our existing Flash routine. All the
> TCL and settings files have been recreated from Vitis logs. We are
> following workflow #1 only and have not implemented workflow 2 for this
> part yet. As a side note, we are using https://www.pyinvoke.org/ to
> automate tasks which helps us to write more Python instead of Bash.
>
> I do believe that all these things must be much better documented, so that
> we spend time somewhere else. When our current workflow is stable, we will
> try to open source as much as we can.
>
> Good luck with porting and let me know if you have any questions.
>
> Stanislav
>
>
> On Wed, Nov 8, 2023 at 3:36 PM Florian Sommerfeld <
>
> fsommerfeld at stud.hs-bremen.de> wrote:
> > Hello Stanislav,
> > I am currently researching on how to get RTEMS up and running on a Zybo
> > Z7-20 Zynq-7000 ARM/FPGA Board (should be rather similar to your Arty
> > Z7) and found your question in the RTEMS users mail archive:
> > https://www.mail-archive.com/users@rtems.org/msg03248.html
> > Did you ever manage to run RTEMS on your Z7-20 board? I was able to use
> > the xilinx_zynq_zedboard BSP to build the RTEMS 5 hello world program,
> > but I am having a hard time on how to actually get it onto the board.
> > Any help is highly appreciated.
> >
> > Sincerely,
> > Florian