disable DCache on RTEMS SMP

[Sebastian Huber]

On 22.05.24 17:53, Sebastian Huber wrote:
> On 19.04.24 08:45, Sebastian Huber wrote:
>> Hello Stéphane,
>>
>> the rtems_cache_disable_data() has no real use case. It is quite 
>> difficult to implement and it is not unusual that its implementation 
>> is broken. I think on RTEMS 6 it should work for this BSP. However, I 
>> am not sure if the atomic operations work, if you disable the data 
>> cache. Without atomic operations, you will have unpredictable 
>> behaviour in SMP configurations.
>>
>> You can statically place data in a non-cacheable area with a section 
>> attribute:
>>
>> #include <bsp/linker-symbols.h>
>>
>> BSP_NOCACHE_SECTION char nocache[123];
> 
> The rtems_cache_disable_data() for the Zynq 7000 BSPs was definitely 
> broken. I fixed it here:
> 
> https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/44
> 
> I would still not use this function in a real application.

Actually, there was bug in the fix, so it still didn't work. I managed 
to disable the L1 and L2 caches, however, afterwards I got not that far. 
On the Cortex-A cores it seems at least the L1 data cache is required to 
provide support for atomic operations:

https://stackoverflow.com/questions/76207164/disabled-dcache-will-prevent-atomic-flag-from-being-set

So, I suggest to do this for the cache manager implementation:

* Make the rtems_cache_disable_data() directive a nop.

* Issue a fatal error if someone calls rtems_cache_disable_data().

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