change log for rtems (2010-12-16)

rtems-vc at rtems.org rtems-vc at rtems.org
Thu Dec 16 14:10:29 UTC 2010


 *sh*:
2010-12-16	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* configure.ac, include/bspopts.h.in: More options.
	* include/lpc32xx.h: Added watchdog definitions.
	* include/mmu.h, misc/mmu.c: Added const qualifier.
	* startup/bspreset.c: Use watchdog reset.

M   1.23  c/src/lib/libbsp/arm/lpc32xx/ChangeLog
M    1.9  c/src/lib/libbsp/arm/lpc32xx/configure.ac
M    1.8  c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
M   1.12  c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
M    1.4  c/src/lib/libbsp/arm/lpc32xx/include/mmu.h
M    1.2  c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c
M    1.2  c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/ChangeLog:1.22 rtems/c/src/lib/libbsp/arm/lpc32xx/ChangeLog:1.23
--- rtems/c/src/lib/libbsp/arm/lpc32xx/ChangeLog:1.22	Fri Dec  3 04:13:07 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/ChangeLog	Thu Dec 16 07:35:06 2010
@@ -1,3 +1,10 @@
+2010-12-16	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	* configure.ac, include/bspopts.h.in: More options.
+	* include/lpc32xx.h: Added watchdog definitions.
+	* include/mmu.h, misc/mmu.c: Added const qualifier.
+	* startup/bspreset.c: Use watchdog reset.
+
 2010-12-03	Sebastian Huber <sebastian.huber at embedded-brains.de>
 
 	* startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1,

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/configure.ac:1.8 rtems/c/src/lib/libbsp/arm/lpc32xx/configure.ac:1.9
--- rtems/c/src/lib/libbsp/arm/lpc32xx/configure.ac:1.8	Tue Sep 28 09:38:26 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/configure.ac	Thu Dec 16 07:35:06 2010
@@ -86,9 +86,15 @@
 RTEMS_BSPOPTS_SET([LPC32XX_STOP_USB],[*],[1])
 RTEMS_BSPOPTS_HELP([LPC32XX_STOP_USB],[stop USB controller at start-up to avoid DMA interference])
 
+RTEMS_BSPOPTS_SET([LPC32XX_ENABLE_WATCHDOG_RESET],[*],[1])
+RTEMS_BSPOPTS_HELP([LPC32XX_ENABLE_WATCHDOG_RESET],[bsp_reset() will use the watchdog to reset the chip])
+
 RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
 RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
 
+RTEMS_BSPOPTS_SET([TESTS_USE_PRINTK],[*],[1])
+RTEMS_BSPOPTS_HELP([TESTS_USE_PRINTK],[tests use printk() for output])
+
 RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
 RTEMS_BSP_LINKCMDS
 

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in:1.7 rtems/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in:1.8
--- rtems/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in:1.7	Tue Sep 28 09:38:26 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in	Thu Dec 16 07:35:06 2010
@@ -45,6 +45,9 @@
 /* disable cache for read-write data sections */
 #undef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE
 
+/* bsp_reset() will use the watchdog to reset the chip */
+#undef LPC32XX_ENABLE_WATCHDOG_RESET
+
 /* enable RMII for Ethernet */
 #undef LPC32XX_ETHERNET_RMII
 
@@ -95,3 +98,6 @@
 
 /* Define to the version of this package. */
 #undef PACKAGE_VERSION
+
+/* tests use printk() for output */
+#undef TESTS_USE_PRINTK

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h:1.11 rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h:1.12
--- rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h:1.11	Fri Dec  3 03:29:07 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h	Thu Dec 16 07:35:06 2010
@@ -221,6 +221,17 @@
 
 /** @} */
 
+/**
+ * @name Timer Clock Control Register (TIMCLK_CTRL)
+ *
+ * @{
+ */
+
+#define TIMCLK_CTRL_WDT BSP_BIT32(0)
+#define TIMCLK_CTRL_HST BSP_BIT32(1)
+
+/** @} */
+
 #define LPC32XX_RESERVED(a, b, s) (((b) - (a) - sizeof(s)) / 4)
 
 typedef struct {
@@ -259,8 +270,76 @@
 typedef struct {
 } lpc32xx_hs_timer;
 
+/**
+ * @name Watchdog Timer Interrupt Status Register (WDTIM_INT)
+ *
+ * @{
+ */
+
+#define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Control Register (WDTIM_CTRL)
+ *
+ * @{
+ */
+
+#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
+#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
+#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Match Control Register (WDTIM_MCTRL)
+ *
+ * @{
+ */
+
+#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
+#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
+#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
+#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
+#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
+#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
+#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer External Match Control Register (WDTIM_EMR)
+ *
+ * @{
+ */
+
+#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
+#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
+#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
+
+/** @} */
+
+/**
+ * @name Watchdog Timer Reset Source Register (WDTIM_RES)
+ *
+ * @{
+ */
+
+#define WDTTIM_RES_WDT BSP_BIT32(0)
+
+/** @} */
+
 typedef struct {
-} lpc32xx_wdg_timer;
+  uint32_t intr;
+  uint32_t ctrl;
+  uint32_t counter;
+  uint32_t mctrl;
+  uint32_t match0;
+  uint32_t emr;
+  uint32_t pulse;
+  uint32_t res;
+} lpc32xx_wdt;
 
 typedef struct {
 } lpc32xx_debug;
@@ -545,8 +624,8 @@
   uint32_t reserved_26 [LPC32XX_RESERVED(0x40034000, 0x40038000, lpc32xx_ms_timer)];
   lpc32xx_hs_timer hs_timer;
   uint32_t reserved_27 [LPC32XX_RESERVED(0x40038000, 0x4003c000, lpc32xx_hs_timer)];
-  lpc32xx_wdg_timer wdg_timer;
-  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdg_timer)];
+  lpc32xx_wdt wdt;
+  uint32_t reserved_28 [LPC32XX_RESERVED(0x4003c000, 0x40040000, lpc32xx_wdt)];
   lpc32xx_debug debug;
   uint32_t reserved_29 [LPC32XX_RESERVED(0x40040000, 0x40044000, lpc32xx_debug)];
   lpc_timer timer_0;

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h:1.3 rtems/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h:1.4
--- rtems/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h:1.3	Tue Sep 28 09:38:26 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h	Thu Dec 16 07:35:06 2010
@@ -56,8 +56,8 @@
   (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
 
 void lpc32xx_set_translation_table_entries(
-  void *begin,
-  void *end,
+  const void *begin,
+  const void *end,
   uint32_t section_flags
 );
 

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c:1.1 rtems/c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c:1.1	Tue Sep 28 09:38:26 2010
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/misc/mmu.c	Thu Dec 16 07:35:06 2010
@@ -23,8 +23,8 @@
 #include <bsp/mmu.h>
 
 void lpc32xx_set_translation_table_entries(
-  void *begin,
-  void *end,
+  const void *begin,
+  const void *end,
   uint32_t section_flags
 )
 {

diff -u rtems/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c:1.1 rtems/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c:1.2
--- rtems/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c:1.1	Tue Dec 15 09:20:47 2009
+++ rtems/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c	Thu Dec 16 07:35:06 2010
@@ -7,24 +7,39 @@
  */
 
 /*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems at embedded-brains.de>
+ * Copyright (c) 2009-2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems at embedded-brains.de>
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
  * http://www.rtems.com/license/LICENSE.
  */
 
-#include <rtems.h>
-
+#include <bspopts.h>
 #include <bsp/bootcard.h>
+#include <bsp/lpc32xx.h>
+
+static void watchdog_reset(void)
+{
+  #ifdef LPC32XX_ENABLE_WATCHDOG_RESET
+    LPC32XX_TIMCLK_CTRL |= TIMCLK_CTRL_WDT;
+    lpc32xx.wdt.mctrl |= WDTTIM_MCTRL_M_RES1 | WDTTIM_MCTRL_M_RES2;
+    lpc32xx.wdt.emr = WDTTIM_EMR_MATCH_CTRL_SET(lpc32xx.wdt.emr, 0x2);
+    lpc32xx.wdt.ctrl |= WDTTIM_CTRL_COUNT_ENAB;
+    lpc32xx.wdt.match0 = 1;
+    lpc32xx.wdt.counter = 0;
+  #endif
+}
 
 void bsp_reset( void)
 {
+  watchdog_reset();
+
   while (true) {
     /* Do nothing */
   }


 *sh*:
2010-12-16	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* shared/lpc/include/lpc-i2s.h: Documentation.  Fixed defines.
	* shared/lpc/include/lpc-timer.h: Documentation.
	* shared/lpc/network/lpc-ethernet.c: Added support for 10MBit/s links.

M   1.85  c/src/lib/libbsp/arm/ChangeLog
M    1.2  c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h
M    1.3  c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
M    1.4  c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c

diff -u rtems/c/src/lib/libbsp/arm/ChangeLog:1.84 rtems/c/src/lib/libbsp/arm/ChangeLog:1.85
--- rtems/c/src/lib/libbsp/arm/ChangeLog:1.84	Fri Dec  3 04:09:59 2010
+++ rtems/c/src/lib/libbsp/arm/ChangeLog	Thu Dec 16 07:35:26 2010
@@ -1,3 +1,9 @@
+2010-12-16	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	* shared/lpc/include/lpc-i2s.h: Documentation.  Fixed defines.
+	* shared/lpc/include/lpc-timer.h: Documentation.
+	* shared/lpc/network/lpc-ethernet.c: Added support for 10MBit/s links.
+
 2010-12-03	Sebastian Huber <sebastian.huber at embedded-brains.de>
 
 	* shared/startup/linkcmds.base: Split up fast region.

diff -u rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h:1.1 rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h:1.2
--- rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h:1.1	Fri Dec  3 03:23:52 2010
+++ rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h	Thu Dec 16 07:35:26 2010
@@ -30,9 +30,10 @@
 #endif
 
 /**
- * @defgroup lpc_dma I2S Support
+ * @defgroup lpc_i2s I2S Support
  *
- * @ingroup lpc
+ * @ingroup lpc24xx
+ * @ingroup lpc32xx
  *
  * @brief I2S support.
  *
@@ -117,8 +118,8 @@
  */
 
 #define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9)
-#define LPC32XX_I2S_RATE_X_DIVIDER BSP_FLD32(val, 0, 7)
-#define LPC32XX_I2S_RATE_Y_DIVIDER BSP_FLD32(val, 8, 15)
+#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7)
+#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15)
 
 /** @} */
 

diff -u rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h:1.2 rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h:1.3
--- rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h:1.2	Fri Apr  9 07:22:57 2010
+++ rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h	Thu Dec 16 07:35:26 2010
@@ -31,7 +31,8 @@
 /**
  * @defgroup lpc_timer Timer Support
  *
- * @ingroup lpc
+ * @ingroup lpc24xx
+ * @ingroup lpc32xx
  *
  * @brief Timer support.
  *

diff -u rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c:1.3 rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c:1.4
--- rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c:1.3	Fri Apr  9 15:24:57 2010
+++ rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c	Thu Dec 16 07:35:26 2010
@@ -47,6 +47,7 @@
 #include <bsp.h>
 #include <bsp/irq.h>
 #include <bsp/lpc-ethernet-config.h>
+#include <bsp/utility.h>
 
 #include <rtems/status-checks.h>
 
@@ -60,6 +61,9 @@
   #define LPC_ETH_CONFIG_TX_BUF_SIZE 1518U
 #endif
 
+#define DEFAULT_PHY 0
+#define WATCHDOG_TIMEOUT 5
+
 typedef struct {
   uint32_t start;
   uint32_t control;
@@ -216,6 +220,35 @@
 #define ETH_STAT_RX_ACTIVE 0x00000001U
 #define ETH_STAT_TX_ACTIVE 0x00000002U
 
+/* ETH_MAC2 */
+
+#define ETH_MAC2_FULL_DUPLEX BSP_BIT32(8)
+
+/* ETH_SUPP */
+
+#define ETH_SUPP_SPEED BSP_BIT32(8)
+
+/* ETH_MCFG */
+
+#define ETH_MCFG_CLOCK_SELECT(val) BSP_FLD32(val, 2, 4)
+
+/* ETH_MCMD */
+
+#define ETH_MCMD_READ BSP_BIT32(0)
+#define ETH_MCMD_SCAN BSP_BIT32(1)
+
+/* ETH_MADR */
+
+#define ETH_MADR_REG(val) BSP_FLD32(val, 0, 4)
+#define ETH_MADR_PHY(val) BSP_FLD32(val, 8, 12)
+
+/* ETH_MIND */
+
+#define ETH_MIND_BUSY BSP_BIT32(0)
+#define ETH_MIND_SCANNING BSP_BIT32(1)
+#define ETH_MIND_NOT_VALID BSP_BIT32(2)
+#define ETH_MIND_MII_LINK_FAIL BSP_BIT32(3)
+
 /* Events */
 
 #define LPC_ETH_EVENT_INITIALIZE RTEMS_EVENT_1
@@ -266,8 +299,9 @@
 
 typedef struct {
   struct arpcom arpcom;
-  struct rtems_mdio_info mdio_info;
   lpc_eth_state state;
+  struct rtems_mdio_info mdio;
+  uint32_t anlpar;
   rtems_id receive_task;
   rtems_id transmit_task;
   unsigned rx_unit_count;
@@ -1041,6 +1075,80 @@
   (void) rtems_task_delete(RTEMS_SELF);
 }
 
+static void lpc_eth_mdio_wait_for_not_busy(void)
+{
+  while ((lpc_eth->mind & ETH_MIND_BUSY) != 0) {
+    rtems_task_wake_after(2);
+  }
+}
+
+static uint32_t lpc_eth_mdio_read_anlpar(void)
+{
+  uint32_t madr = ETH_MADR_REG(MII_ANLPAR) | ETH_MADR_PHY(DEFAULT_PHY);
+  uint32_t anlpar = 0;
+
+  if (lpc_eth->madr != madr) {
+    lpc_eth->madr = madr;
+  }
+
+  if (lpc_eth->mcmd != ETH_MCMD_READ) {
+    lpc_eth->mcmd = 0;
+    lpc_eth->mcmd = ETH_MCMD_READ;
+  }
+
+  lpc_eth_mdio_wait_for_not_busy();
+
+  anlpar = lpc_eth->mrdd;
+
+  /* Start next read */
+  lpc_eth->mcmd = 0;
+  lpc_eth->mcmd = ETH_MCMD_READ;
+
+  return anlpar;
+}
+
+static int lpc_eth_mdio_read(
+  int phy __attribute__((unused)),
+  void *arg __attribute__((unused)),
+  unsigned reg,
+  uint32_t *val
+)
+{
+  int eno = 0;
+
+  if (phy == -1 || phy == 0) {
+    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
+    lpc_eth->mcmd = 0;
+    lpc_eth->mcmd = ETH_MCMD_READ;
+    lpc_eth_mdio_wait_for_not_busy();
+    *val = lpc_eth->mrdd;
+  } else {
+    eno = EINVAL;
+  }
+
+  return eno;
+}
+
+static int lpc_eth_mdio_write(
+  int phy __attribute__((unused)),
+  void *arg __attribute__((unused)),
+  unsigned reg,
+  uint32_t val
+)
+{
+  int eno = 0;
+
+  if (phy == -1 || phy == 0) {
+    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
+    lpc_eth->mwtd = val;
+    lpc_eth_mdio_wait_for_not_busy();
+  } else {
+    eno = EINVAL;
+  }
+
+  return eno;
+}
+
 static void lpc_eth_interface_init(void *arg)
 {
   rtems_status_code sc = RTEMS_SUCCESSFUL;
@@ -1060,6 +1168,7 @@
     lpc_eth->mac1 = 0x0;
 
     /* Initialize PHY */
+    lpc_eth->mcfg = ETH_MCFG_CLOCK_SELECT(0x7);
     /* TODO */
 
     /* Reinitialize registers */
@@ -1068,7 +1177,7 @@
     lpc_eth->ipgr = 0x12;
     lpc_eth->clrt = 0x370f;
     lpc_eth->maxf = 0x0600;
-    lpc_eth->supp = 0x0100;
+    lpc_eth->supp = ETH_SUPP_SPEED;
     lpc_eth->test = 0;
     #ifdef LPC_ETH_CONFIG_RMII
       lpc_eth->command = 0x0600;
@@ -1140,10 +1249,18 @@
   }
 }
 
-static void lpc_eth_interface_stats(const lpc_eth_driver_entry *e)
+static void lpc_eth_interface_stats(lpc_eth_driver_entry *e)
 {
+  int media = IFM_MAKEWORD(0, 0, 0, 0);
+  int eno = rtems_mii_ioctl(&e->mdio, e, SIOCGIFMEDIA, &media);
+
   rtems_bsdnet_semaphore_release();
 
+  if (eno == 0) {
+    rtems_ifmedia2str(media, NULL, 0);
+    printf("\n");
+  }
+
   printf("received frames:                     %u\n", e->received_frames);
   printf("receive interrupts:                  %u\n", e->receive_interrupts);
   printf("transmitted frames:                  %u\n", e->transmitted_frames);
@@ -1181,7 +1298,7 @@
   switch (command)  {
     case SIOCGIFMEDIA:
     case SIOCSIFMEDIA:
-      rtems_mii_ioctl(&e->mdio_info, e, (int) command, (int *) data);
+      rtems_mii_ioctl(&e->mdio, e, command, (int *) data);
       break;
     case SIOCGIFADDR:
     case SIOCSIFADDR:
@@ -1220,7 +1337,40 @@
 
 static void lpc_eth_interface_watchdog(struct ifnet *ifp __attribute__((unused)))
 {
-  LPC_ETH_PRINTF("%s\n", __func__);
+  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
+  uint32_t anlpar = lpc_eth_mdio_read_anlpar();
+
+  if (e->anlpar != anlpar) {
+    bool full_duplex = false;
+    bool speed = false;
+
+    e->anlpar = anlpar;
+
+    if ((anlpar & ANLPAR_TX_FD) != 0) {
+      full_duplex = true;
+      speed = true;
+    } else if ((anlpar & ANLPAR_T4) != 0) {
+      speed = true;
+    } else if ((anlpar & ANLPAR_TX) != 0) {
+      speed = true;
+    } else if ((anlpar & ANLPAR_10_FD) != 0) {
+      full_duplex = true;
+    }
+
+    if (full_duplex) {
+      lpc_eth->mac2 |= ETH_MAC2_FULL_DUPLEX;
+    } else {
+      lpc_eth->mac2 &= ~ETH_MAC2_FULL_DUPLEX;
+    }
+
+    if (speed) {
+      lpc_eth->supp |= ETH_SUPP_SPEED;
+    } else {
+      lpc_eth->supp &= ~ETH_SUPP_SPEED;
+    }
+  }
+
+  ifp->if_timer = WATCHDOG_TIMEOUT;
 }
 
 static unsigned lpc_eth_fixup_unit_count(int count, int default_value, int max)
@@ -1261,6 +1411,12 @@
     RTEMS_DO_CLEANUP(cleanup, "already attached");
   }
 
+  /* MDIO */
+  e->mdio.mdio_r = lpc_eth_mdio_read;
+  e->mdio.mdio_w = lpc_eth_mdio_write;
+  e->mdio.has_gmii = 0;
+  e->anlpar = 0;
+
   /* Interrupt number */
   config->irno = LPC_ETH_CONFIG_INTERRUPT;
 



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