change log for rtems (2010-05-13)
rtems-vc at rtems.org
rtems-vc at rtems.org
Thu May 13 20:10:45 UTC 2010
*joel*:
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
* Makefile.am, configure.ac: rbtx4925, rbtx4938, and hurricane had very
similar versions of exception. Now all use shared/irq/exception.S
* startup/exception.S: Removed.
M 1.51 c/src/lib/libbsp/mips/hurricane/ChangeLog
M 1.16 c/src/lib/libbsp/mips/hurricane/Makefile.am
M 1.10 c/src/lib/libbsp/mips/hurricane/configure.ac
R 1.5 c/src/lib/libbsp/mips/hurricane/startup/exception.S
diff -u rtems/c/src/lib/libbsp/mips/hurricane/ChangeLog:1.50 rtems/c/src/lib/libbsp/mips/hurricane/ChangeLog:1.51
--- rtems/c/src/lib/libbsp/mips/hurricane/ChangeLog:1.50 Thu May 13 13:08:11 2010
+++ rtems/c/src/lib/libbsp/mips/hurricane/ChangeLog Thu May 13 14:22:42 2010
@@ -1,5 +1,11 @@
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+ * Makefile.am, configure.ac: rbtx4925, rbtx4938, and hurricane had very
+ similar versions of exception. Now all use shared/irq/exception.S
+ * startup/exception.S: Removed.
+
+2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+
* startup/exception.S: Minor changes to make more similar to the shared
version.
diff -u rtems/c/src/lib/libbsp/mips/hurricane/Makefile.am:1.15 rtems/c/src/lib/libbsp/mips/hurricane/Makefile.am:1.16
--- rtems/c/src/lib/libbsp/mips/hurricane/Makefile.am:1.15 Thu Oct 2 16:38:26 2008
+++ rtems/c/src/lib/libbsp/mips/hurricane/Makefile.am Thu May 13 14:22:42 2010
@@ -36,8 +36,8 @@
../../shared/bsppredriverhook.c startup/bspstart.c \
../../shared/bootcard.c ../../shared/sbrk.c \
../../shared/gnatinstallhandler.c ../../shared/setvec.c \
- startup/inittlb.c \
- startup/idtmem.S startup/idttlb.S startup/exception.S
+ startup/inittlb.c startup/idtmem.S startup/idttlb.S \
+ ../shared/startup/exception.S startup/usc.S
# clock
libbsp_a_SOURCES += clock/ckinit.c
# console
diff -u rtems/c/src/lib/libbsp/mips/hurricane/configure.ac:1.9 rtems/c/src/lib/libbsp/mips/hurricane/configure.ac:1.10
--- rtems/c/src/lib/libbsp/mips/hurricane/configure.ac:1.9 Sat Nov 28 00:28:40 2009
+++ rtems/c/src/lib/libbsp/mips/hurricane/configure.ac Thu May 13 14:22:42 2010
@@ -16,6 +16,14 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
+RTEMS_BSPOPTS_SET([BSP_HAS_USC320],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_HAS_USC320],
+[This BSP has a V3 USC320 system controller chip.])
+
+RTEMS_BSPOPTS_SET([BSP_HAS_RM52xx],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_HAS_RM52xx],
+[This BSP has a RM52xx compatible CPU.])
+
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
# Explicitly list all Makefiles here
*joel*:
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
* configure.ac: rbtx4925, rbtx4938, and hurricane had very similar
versions of exception. Now all use shared/irq/exception.S
M 1.47 c/src/lib/libbsp/mips/rbtx4925/ChangeLog
M 1.10 c/src/lib/libbsp/mips/rbtx4925/configure.ac
diff -u rtems/c/src/lib/libbsp/mips/rbtx4925/ChangeLog:1.46 rtems/c/src/lib/libbsp/mips/rbtx4925/ChangeLog:1.47
--- rtems/c/src/lib/libbsp/mips/rbtx4925/ChangeLog:1.46 Thu May 13 13:08:33 2010
+++ rtems/c/src/lib/libbsp/mips/rbtx4925/ChangeLog Thu May 13 14:22:44 2010
@@ -1,5 +1,10 @@
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+ * configure.ac: rbtx4925, rbtx4938, and hurricane had very similar
+ versions of exception. Now all use shared/irq/exception.S
+
+2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+
* Makefile.am: rbtx4925 and rbtx4938 had copies of the same file with
only minor differences. Both now use shared/irq/exception.S
* startup/exception.S: Removed.
diff -u rtems/c/src/lib/libbsp/mips/rbtx4925/configure.ac:1.9 rtems/c/src/lib/libbsp/mips/rbtx4925/configure.ac:1.10
--- rtems/c/src/lib/libbsp/mips/rbtx4925/configure.ac:1.9 Sat Nov 28 00:28:40 2009
+++ rtems/c/src/lib/libbsp/mips/rbtx4925/configure.ac Thu May 13 14:22:44 2010
@@ -16,6 +16,10 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
+RTEMS_BSPOPTS_SET([BSP_HAS_TX49xx],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_HAS_TX49xx],
+[This BSP has a RM52xx compatible CPU.])
+
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
# Explicitly list all Makefiles here
*joel*:
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
* shared/irq/exception.S: rbtx4925, rbtx4938, and hurricane had very
similar versions of exception. Now all use shared/irq/exception.S
M 1.36 c/src/lib/libbsp/mips/ChangeLog
M 1.2 c/src/lib/libbsp/mips/shared/irq/exception.S
diff -u rtems/c/src/lib/libbsp/mips/ChangeLog:1.35 rtems/c/src/lib/libbsp/mips/ChangeLog:1.36
--- rtems/c/src/lib/libbsp/mips/ChangeLog:1.35 Thu May 13 13:08:38 2010
+++ rtems/c/src/lib/libbsp/mips/ChangeLog Thu May 13 14:22:46 2010
@@ -1,5 +1,10 @@
2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+ * shared/irq/exception.S: rbtx4925, rbtx4938, and hurricane had very
+ similar versions of exception. Now all use shared/irq/exception.S
+
+2010-05-13 Joel Sherrill <joel.sherrill at oarcorp.com>
+
* shared/irq/exception.S: New file.
2010-04-28 Joel Sherrill <joel.sherrilL at OARcorp.com>
diff -u rtems/c/src/lib/libbsp/mips/shared/irq/exception.S:1.1 rtems/c/src/lib/libbsp/mips/shared/irq/exception.S:1.2
--- rtems/c/src/lib/libbsp/mips/shared/irq/exception.S:1.1 Thu May 13 13:08:38 2010
+++ rtems/c/src/lib/libbsp/mips/shared/irq/exception.S Thu May 13 14:22:46 2010
@@ -23,7 +23,7 @@
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
*
- * COPYRIGHT (c) 1989-1999.
+ * COPYRIGHT (c) 1989-2010.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -32,20 +32,14 @@
*
* $Id$
*/
-/* @(#)exception.S 7/27/04 1.00 */
+#include <bspopts.h>
+#include <rtems/asm.h>
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
-
-
-#define FRAME(name,frm_reg,offset,ret_reg) \
- .globl name; \
- .ent name; \
-name:; \
- .frame frm_reg,offset,ret_reg
-#define ENDFRAME(name) \
- .end name
-
+#if BSP_HAS_USC320
+ #include <usc.h>
+#endif
#if __mips == 3
/* 64 bit register operations */
@@ -148,7 +142,6 @@
ori k0,k0,0xf500
sw k1,(k0)
#endif
-
mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */
nop
and k1,k0,CAUSE_EXCMASK
@@ -163,8 +156,13 @@
mfc0 k1,C0_SR
nop
and k0,k1
+#if HAS_RM52xx
+ and k0,CAUSE_IPMASK
+#elif HAS_TX49xx
and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3)
- beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */
+#endif
+ /* external interrupt not enabled, ignore */
+ beq k0,zero,_ISR_Handler_quick_exit
nop
/* For debugging interrupts, clear EXL to allow breakpoints */
@@ -250,17 +248,20 @@
add t1,t1,1
sw t1,_Thread_Dispatch_disable_level
-
- /* DEBUG - Add the following code to disable interrupts and clear EXL in status register, this will
- allow memory exceptions to occur while servicing the current interrupt */
+ /* DEBUG - Add the following code to disable interrupts and clear
+ * EXL in status register, this will allow memory
+ * exceptions to occur while servicing the current interrupt
+ */
#if 0
- li t0,~CAUSE_IP2_MASK /* Disable interrupts from internal interrupt controller */
+ /* Disable interrupts from internal interrupt controller */
+ li t0,~CAUSE_IP2_MASK
mfc0 t1,C0_SR
nop
and t1,t0
mtc0 t1,C0_SR
nop
- li t0,~SR_EXL /* Clear EXL in status register to allow memory exceptions to occur */
+ /* Clear EXL in status register to allow memory exceptions to occur */
+ li t0,~SR_EXL
mfc0 t1,C0_SR
nop
and t1,t0
@@ -284,7 +285,8 @@
or t1,t0
mtc0 t1,C0_SR
nop
- li t0,CAUSE_IP2_MASK /* Enable interrupts from internal interrupt controller */
+ /* Enable interrupts from internal interrupt controller */
+ li t0,CAUSE_IP2_MASK
mfc0 t1,C0_SR
nop
or t1,t0
@@ -386,7 +388,6 @@
mtc0 t0, C0_SR
NOP
-
/*
* prepare to get out of interrupt
* return from interrupt (maybe to _ISR_Dispatch)
@@ -437,6 +438,39 @@
nop
+#if BSP_HAS_USC320
+ /* Interrupts from USC320 are serviced here */
+ .global USC_isr
+ .extern Clock_isr
+USC_isr:
+ /* check if it's a USC320 heartbeat interrupt */
+ la k0,INT_STAT /* read INT_STAT register */
+ lw k0,(k0)
+ nop /* reading from external device */
+ sll k0,(31-21) /* test bit 21 (HBI) */
+
+ bgez k0,USC_isr2 /* branch if not a heartbeat interrupt */
+ NOP
+
+ /* clear the heartbeat interrupt */
+ la k0,INT_STAT
+ li t0,HBI_MASK
+ sw t0,(k0)
+ /* wait for interrupt to clear */
+USC_isr1:
+ la k0,INT_STAT /* read INT_STAT register */
+ lw k0,(k0)
+ nop /* reading from external device */
+ sll k0,(31-21) /* test bit 21 (HBI) */
+ bltz k0,USC_isr1 /* branch if bit set */
+ nop
+ j Clock_isr /* Jump to clock isr */
+ nop
+USC_isr2:
+ j ra /* no serviceable interrupt, return without doing anything */
+ nop
+#endif
+
#if 0
.global int7_isr
.extern Interrupt_7_isr
@@ -467,7 +501,7 @@
FRAME(_BRK_Handler,sp,0,ra)
.set noreorder
-#ifdef USC
+#if BSP_HAS_USC320
la k0,INT_CFG3 /* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */
lw k1,(k0)
li k0,~HBI_MASK
--
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