change log for rtems (2011-02-16)

rtems-vc at rtems.org rtems-vc at rtems.org
Wed Feb 16 09:10:25 UTC 2011


 *sh*:
2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* libchip/serial/ns16550.c: Revert previous commit and extend existing
	mechanic.

M  1.540  c/src/ChangeLog
M   1.49  c/src/libchip/serial/ns16550.c

diff -u rtems/c/src/ChangeLog:1.539 rtems/c/src/ChangeLog:1.540
--- rtems/c/src/ChangeLog:1.539	Tue Feb 15 17:25:24 2011
+++ rtems/c/src/ChangeLog	Wed Feb 16 02:25:00 2011
@@ -1,3 +1,8 @@
+2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	* libchip/serial/ns16550.c: Revert previous commit and extend existing
+	mechanic.
+
 2011-02-15	Jennifer Averett
 
 	* libchip/serial/ns16550.c, libchip/serial/ns16550_p.h: Support i386

diff -u rtems/c/src/libchip/serial/ns16550.c:1.48 rtems/c/src/libchip/serial/ns16550.c:1.49
--- rtems/c/src/libchip/serial/ns16550.c:1.48	Tue Feb 15 17:25:24 2011
+++ rtems/c/src/libchip/serial/ns16550.c	Wed Feb 16 02:25:00 2011
@@ -39,18 +39,16 @@
 
 #include "ns16550_p.h"
 
-#ifdef BSP_FEATURE_IRQ_EXTENSION
+#if defined(BSP_FEATURE_IRQ_EXTENSION)
   #include <bsp/irq.h>
-#elif defined BSP_FEATURE_IRQ_LEGACY
+#elif defined(BSP_FEATURE_IRQ_LEGACY)
   #include <bsp/irq.h>
-#elif defined __PPC__
+#elif defined(__PPC__) || defined(__i386__)
   #include <bsp/irq.h>
   #define BSP_FEATURE_IRQ_LEGACY
   #ifdef BSP_SHARED_HANDLER_SUPPORT
     #define BSP_FEATURE_IRQ_LEGACY_SHARED_HANDLER_SUPPORT
   #endif
-#elif defined(__i386__)
-  #include <bsp/irq.h>
 #endif
 
 /*
@@ -474,6 +472,7 @@
   return 0;
 }
 
+#if defined(BSP_FEATURE_IRQ_EXTENSION) || defined(BSP_FEATURE_IRQ_LEGACY)
 
 /**
  * @brief Process interrupt.
@@ -522,7 +521,6 @@
     }
   } while ((get( port, NS16550_INTERRUPT_ID) & SP_IID_0) == 0);
 }
-#if defined(BSP_FEATURE_IRQ_EXTENSION) || defined(BSP_FEATURE_IRQ_LEGACY)
 #endif
 
 /**
@@ -580,12 +578,14 @@
   (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, mask);
 }
 
- NS16550_STATIC rtems_isr ns16550_isr(void *arg)
- {
+#if defined(BSP_FEATURE_IRQ_EXTENSION) || defined(BSP_FEATURE_IRQ_LEGACY)
+  NS16550_STATIC rtems_isr ns16550_isr(void *arg)
+  {
     int minor = (int) arg;
 
     ns16550_process( minor);
- }
+  }
+#endif
 
 /*
  *  ns16550_initialize_interrupts
@@ -595,8 +595,8 @@
 NS16550_STATIC void ns16550_initialize_interrupts( int minor)
 {
 #if defined(BSP_FEATURE_IRQ_EXTENSION) || defined(BSP_FEATURE_IRQ_LEGACY)
-#endif
   console_tbl *c = &Console_Port_Tbl [minor];
+#endif
   console_data *d = &Console_Port_Data [minor];
 
   d->bActive = false;
@@ -648,23 +648,6 @@
         rtems_fatal_error_occurred( 0xdeadbeef);
       }
     }
-  #elif defined(__i386__)
-    {
-      int rv = 0;
-      rtems_irq_connect_data cd = {
-        c->ulIntVector,
-        ns16550_isr,
-        (void *) minor,
-        NULL,
-        NULL,
-        NULL
-      };
-      rv = BSP_install_rtems_irq_handler( &cd);
-      if (rv == 0) {
-        printk( "%s: Error: Install interrupt handler\n", __func__);
-        rtems_fatal_error_occurred( 0xdeadbeef);
-      }
-    }
   #endif
 }
 


 *sh*:
2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* rtems/powerpc/registers.h: Added FSL_EIS_ATBL, FSL_EIS_ATBL, and
	FSL_EIS_SPEFSCR defines.

M  1.163  cpukit/score/cpu/powerpc/ChangeLog
M   1.37  cpukit/score/cpu/powerpc/rtems/powerpc/registers.h

diff -u rtems/cpukit/score/cpu/powerpc/ChangeLog:1.162 rtems/cpukit/score/cpu/powerpc/ChangeLog:1.163
--- rtems/cpukit/score/cpu/powerpc/ChangeLog:1.162	Tue Feb 15 01:45:16 2011
+++ rtems/cpukit/score/cpu/powerpc/ChangeLog	Wed Feb 16 02:27:14 2011
@@ -1,3 +1,8 @@
+2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	* rtems/powerpc/registers.h: Added FSL_EIS_ATBL, FSL_EIS_ATBL, and
+	FSL_EIS_SPEFSCR defines.
+
 2011-02-15	Sebastian Huber <sebastian.huber at embedded-brains.de>
 
 	* rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and

diff -u rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.36 rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.37
--- rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.36	Tue Feb 15 01:45:16 2011
+++ rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h	Wed Feb 16 02:27:14 2011
@@ -409,6 +409,15 @@
 #define FSL_EIS_L1CSR0 1010
 #define FSL_EIS_L1CSR1 1011
 
+/* Freescale Book E Implementation Standards (EIS): Timer */
+
+#define FSL_EIS_ATBL 526
+#define FSL_EIS_ATBU 527
+
+/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */
+
+#define FSL_EIS_SPEFSCR 512
+
 /**
  * @brief Default value for the interrupt disable mask.
  *


 *sh*:
2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* shared/include/powerpc-utility.h: Fixed LINKER_SYMBOL() for
	assembler compatibilty.  Added synchronization, cache, and alternate
	time base functions.

M  1.377  c/src/lib/libcpu/powerpc/ChangeLog
M   1.15  c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

diff -u rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.376 rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.377
--- rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.376	Fri Feb 11 07:05:24 2011
+++ rtems/c/src/lib/libcpu/powerpc/ChangeLog	Wed Feb 16 02:33:02 2011
@@ -1,3 +1,9 @@
+2011-02-16	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	* shared/include/powerpc-utility.h: Fixed LINKER_SYMBOL() for
+	assembler compatibilty.  Added synchronization, cache, and alternate
+	time base functions.
+
 2011-02-11	Ralf Corsépius <ralf.corsepius at rtems.org>
 
 	* mpc55xx/include/mpc55xx.h:

diff -u rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.14 rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.15
--- rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.14	Fri Feb 11 03:46:53 2011
+++ rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h	Wed Feb 16 02:33:02 2011
@@ -8,7 +8,7 @@
  */
 
 /*
- * Copyright (c) 2008
+ * Copyright (c) 2008, 2010, 2011
  * Embedded Brains GmbH
  * Obere Lagerstr. 30
  * D-82178 Puchheim
@@ -48,7 +48,7 @@
 
 #include <libcpu/cpuIdent.h>
 
-#define LINKER_SYMBOL(sym) extern char sym []
+#define LINKER_SYMBOL(sym) extern char sym [];
 
 /**
  * @brief Read one byte from @a src.
@@ -211,6 +211,167 @@
   __asm__ volatile ("isync");
 }
 
+static inline void ppc_enforce_in_order_execution_of_io(void)
+{
+  RTEMS_COMPILER_MEMORY_BARRIER();
+
+  __asm__ volatile ("eieio");
+}
+
+static inline void ppc_data_cache_block_flush(void *addr)
+{
+  __asm__ volatile (
+    "dcbf 0, %0"
+    :
+    : "r" (addr)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_flush_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbf %0, %1"
+    :
+    : "b" (base), "r" (offset)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_invalidate(void *addr)
+{
+  __asm__ volatile (
+    "dcbi 0, %0"
+    :
+    : "r" (addr)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_invalidate_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbi %0, %1"
+    :
+    : "b" (base), "r" (offset)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_store(void *addr)
+{
+  __asm__ volatile (
+    "dcbst 0, %0"
+    :
+    : "r" (addr)
+  );
+}
+
+static inline void ppc_data_cache_block_store_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbst %0, %1"
+    :
+    : "b" (base), "r" (offset)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_touch(void *addr)
+{
+  __asm__ volatile (
+    "dcbt 0, %0"
+    :
+    : "r" (addr)
+  );
+}
+
+static inline void ppc_data_cache_block_touch_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbt %0, %1"
+    :
+    : "b" (base), "r" (offset)
+  );
+}
+
+static inline void ppc_data_cache_block_touch_for_store(void *addr)
+{
+  __asm__ volatile (
+    "dcbtst 0, %0"
+    :
+    : "r" (addr)
+  );
+}
+
+static inline void ppc_data_cache_block_touch_for_store_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbtst %0, %1"
+    :
+    : "b" (base), "r" (offset)
+  );
+}
+
+static inline void ppc_data_cache_block_clear_to_zero(void *addr)
+{
+  __asm__ volatile (
+    "dcbz 0, %0"
+    :
+    : "r" (addr)
+    : "memory"
+  );
+}
+
+static inline void ppc_data_cache_block_clear_to_zero_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "dcbz %0, %1"
+    :
+    : "b" (base), "r" (offset)
+    : "memory"
+  );
+}
+
+static inline void ppc_instruction_cache_block_invalidate(void *addr)
+{
+  __asm__ volatile (
+    "icbi 0, %0"
+    :
+    : "r" (addr)
+  );
+}
+
+static inline void ppc_instruction_cache_block_invalidate_2(
+  void *base,
+  void *offset
+)
+{
+  __asm__ volatile (
+    "icbi %0, %1"
+    :
+    : "b" (base), "r" (offset)
+  );
+}
+
 /**
  * @brief Enables external exceptions.
  *
@@ -575,6 +736,41 @@
   PPC_Set_timebase_register(val);
 }
 
+static inline uint32_t ppc_alternate_time_base(void)
+{
+  return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL);
+}
+
+static inline uint32_t ppc_alternate_time_base_upper(void)
+{
+  return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU);
+}
+
+static inline uint64_t ppc_alternate_time_base_64(void)
+{
+  uint32_t atbl;
+  uint32_t atbu_0;
+  uint32_t atbu_1;
+
+  do {
+    atbu_0 = ppc_alternate_time_base_upper();
+    atbl = ppc_alternate_time_base();
+    atbu_1 = ppc_alternate_time_base_upper();
+  } while (atbu_0 != atbu_1);
+
+  return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl);
+}
+
+static inline uint32_t ppc_processor_id(void)
+{
+  return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR);
+}
+
+static inline void ppc_set_processor_id(uint32_t val)
+{
+  PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val);
+}
+
 void ppc_code_copy(void *dest, const void *src, size_t n);
 
 #endif /* ifndef ASM */



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