change log for rtems (2011-06-07)

rtems-vc at rtems.org rtems-vc at rtems.org
Tue Jun 7 09:11:39 UTC 2011


 *sh*:
2011-06-07	Sebastian Huber <sebastian.huber at embedded-brains.de>

	* shared/src/cache_.h: Moved implementation from "cache.c" to here.
	This avoids the function call overhead.
	* shared/src/cache.c: Removed file.
	* Makefile.am: Reflect changes above.

M  1.385  c/src/lib/libcpu/powerpc/ChangeLog
M   1.63  c/src/lib/libcpu/powerpc/Makefile.am
R   1.13  c/src/lib/libcpu/powerpc/shared/src/cache.c
M    1.8  c/src/lib/libcpu/powerpc/shared/src/cache_.h

diff -u rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.384 rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.385
--- rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.384	Tue Jun  7 02:52:59 2011
+++ rtems/c/src/lib/libcpu/powerpc/ChangeLog	Tue Jun  7 03:23:44 2011
@@ -1,5 +1,12 @@
 2011-06-07	Sebastian Huber <sebastian.huber at embedded-brains.de>
 
+	* shared/src/cache_.h: Moved implementation from "cache.c" to here.
+	This avoids the function call overhead.
+	* shared/src/cache.c: Removed file.
+	* Makefile.am: Reflect changes above.
+
+2011-06-07	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
 	* shared/src/cache_.h: Include required header file.
 
 2011-05-19	Sebastian Huber <sebastian.huber at embedded-brains.de>

diff -u rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.62 rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.63
--- rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.62	Thu Dec 30 07:12:03 2010
+++ rtems/c/src/lib/libcpu/powerpc/Makefile.am	Tue Jun  7 03:23:44 2011
@@ -74,7 +74,7 @@
 
 # shared/cache
 noinst_PROGRAMS += shared/cache.rel
-shared_cache_rel_SOURCES = shared/src/cache.c shared/src/cache_.h \
+shared_cache_rel_SOURCES = shared/src/cache_.h \
     ../shared/src/cache_aligned_malloc.c ../shared/src/cache_manager.c \
     ../shared/include/cache.h
 shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/src

diff -u rtems/c/src/lib/libcpu/powerpc/shared/src/cache_.h:1.7 rtems/c/src/lib/libcpu/powerpc/shared/src/cache_.h:1.8
--- rtems/c/src/lib/libcpu/powerpc/shared/src/cache_.h:1.7	Tue Jun  7 02:52:59 2011
+++ rtems/c/src/lib/libcpu/powerpc/shared/src/cache_.h	Tue Jun  7 03:23:44 2011
@@ -6,11 +6,20 @@
  * @brief Header file for the Cache Manager PowerPC support.
  */
 
+/*
+ *  Cache Management Support Routines for the MC68040
+ * Modified for MPC8260 Andy Dachs <a.dachs at sstl.co.uk>
+ * Surrey Satellite Technology Limited (SSTL), 2001
+ *
+ *  $Id$
+ */
+
 #ifndef LIBCPU_POWERPC_CACHE_H
 #define LIBCPU_POWERPC_CACHE_H
 
+#include <rtems.h>
 #include <rtems/powerpc/powerpc.h>
-#include <libcpu/cache.h>
+#include <rtems/powerpc/registers.h>
 
 /* Provide the CPU defines only if we have a cache */
 #if PPC_CACHE_ALIGNMENT != PPC_NO_CACHE_ALIGNMENT
@@ -18,4 +27,254 @@
   #define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
 #endif
 
+/*
+ * CACHE MANAGER: The following functions are CPU-specific.
+ * They provide the basic implementation for the rtems_* cache
+ * management routines. If a given function has no meaning for the CPU,
+ * it does nothing by default.
+ *
+ * FIXME: Some functions simply have not been implemented.
+ */
+
+#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */
+
+/* Helpful macros */
+#define PPC_Get_HID0( _value ) \
+  do { \
+      _value = 0;        /* to avoid warnings */ \
+      __asm__ volatile( \
+          "mfspr %0, 0x3f0;"     /* get HID0 */ \
+          "isync" \
+          : "=r" (_value) \
+          : "0" (_value) \
+      ); \
+  } while (0)
+
+#define PPC_Set_HID0( _value ) \
+  do { \
+      __asm__ volatile( \
+          "isync;" \
+          "mtspr 0x3f0, %0;"     /* load HID0 */ \
+          "isync" \
+          : "=r" (_value) \
+          : "0" (_value) \
+      ); \
+  } while (0)
+
+static inline void _CPU_cache_enable_data(void)
+{
+  uint32_t   value;
+  PPC_Get_HID0( value );
+  value |= HID0_DCE;        /* set DCE bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+  uint32_t   value;
+  PPC_Get_HID0( value );
+  value &= ~HID0_DCE;        /* clear DCE bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value |= HID0_DCI;        /* set data flash invalidate bit */
+  PPC_Set_HID0( value );
+  value &= ~HID0_DCI;        /* clear data flash invalidate bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_freeze_data(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value |= HID0_DLOCK;        /* set data cache lock bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value &= ~HID0_DLOCK;        /* set data cache lock bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_flush_entire_data(void)
+{
+  /*
+   * FIXME: how can we do this?
+   */
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+  uint32_t   value;
+  PPC_Get_HID0( value );
+  value |= 0x00008000;       /* Set ICE bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+  uint32_t   value;
+  PPC_Get_HID0( value );
+  value &= 0xFFFF7FFF;       /* Clear ICE bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value |= HID0_ICFI;        /* set data flash invalidate bit */
+  PPC_Set_HID0( value );
+  value &= ~HID0_ICFI;        /* clear data flash invalidate bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value |= HID0_ILOCK;        /* set instruction cache lock bit */
+  PPC_Set_HID0( value );
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+  uint32_t  value;
+  PPC_Get_HID0( value );
+  value &= ~HID0_ILOCK;        /* set instruction cache lock bit */
+  PPC_Set_HID0( value );
+}
+
+#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
+
+#define mtspr(_spr,_reg) \
+  __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
+#define isync \
+  __asm__ volatile ("isync\n"::)
+
+static inline void _CPU_cache_flush_entire_data(void) {}
+static inline void _CPU_cache_invalidate_entire_data(void) {}
+static inline void _CPU_cache_freeze_data(void) {}
+static inline void _CPU_cache_unfreeze_data(void) {}
+
+static inline void _CPU_cache_enable_data(void)
+{
+  uint32_t   r1;
+  r1 = (0x2<<24);
+  mtspr( 568, r1 );
+  isync;
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+  uint32_t   r1;
+  r1 = (0x4<<24);
+  mtspr( 568, r1 );
+  isync;
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void) {}
+static inline void _CPU_cache_freeze_instruction(void) {}
+static inline void _CPU_cache_unfreeze_instruction(void) {}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+  uint32_t   r1;
+  r1 = (0x2<<24);
+  mtspr( 560, r1 );
+  isync;
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+  uint32_t   r1;
+  r1 = (0x4<<24);
+  mtspr( 560, r1 );
+  isync;
+}
+
+#else
+
+#warning Most cache functions are not implemented
+
+static inline void _CPU_cache_flush_entire_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_freeze_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_enable_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+	/* Void */
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+	/* Void */
+}
+
+#endif
+
+static inline void _CPU_cache_invalidate_1_data_line(const void *addr)
+{
+  __asm__ volatile ( "dcbi 0,%0" :: "r" (addr) : "memory" );
+}
+
+static inline void _CPU_cache_flush_1_data_line(const void *addr)
+{
+  __asm__ volatile ( "dcbf 0,%0" :: "r" (addr) : "memory" );
+}
+
+
+static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+{
+  __asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory");
+}
+
 #endif /* LIBCPU_POWERPC_CACHE_H */


 *sh*:
2011-06-07	Sebastian Huber <sebastian.huber at embedded-brains.de>

	PR 1811/networking
	* ftpd/ftpd.c: Fixed reply format.

M 1.2847  cpukit/ChangeLog
M   1.25  cpukit/ftpd/ftpd.c

diff -u rtems/cpukit/ChangeLog:1.2846 rtems/cpukit/ChangeLog:1.2847
--- rtems/cpukit/ChangeLog:1.2846	Thu May 26 13:07:07 2011
+++ rtems/cpukit/ChangeLog	Tue Jun  7 04:08:37 2011
@@ -1,3 +1,8 @@
+2011-06-07	Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+	PR 1811/networking
+	* ftpd/ftpd.c: Fixed reply format.
+
 2011-05-26	Jennifer Averett <Jennifer.Averett at OARcorp.com>
 
 	PR 1796/cpukit

diff -u rtems/cpukit/ftpd/ftpd.c:1.24 rtems/cpukit/ftpd/ftpd.c:1.25
--- rtems/cpukit/ftpd/ftpd.c:1.24	Mon Apr  4 12:08:34 2011
+++ rtems/cpukit/ftpd/ftpd.c	Tue Jun  7 04:08:37 2011
@@ -552,12 +552,8 @@
 static void
 send_reply(FTPD_SessionInfo_t  *info, int code, char *text)
 {
-  char const* s = (info->xfer_mode == TYPE_A) ? "\r" : "";
-  /* If a text reply exists, add it to the reply data. */
-  if (text != NULL)
-    fprintf(info->ctrl_fp, "%d %.70s%s\n", code, text, s);
-  else
-    fprintf(info->ctrl_fp, "%d%s\n", code, s);
+  text = text != NULL ? text : "";
+  fprintf(info->ctrl_fp, "%d %.70s\r\n", code, text);
   fflush(info->ctrl_fp);
 }
 



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