change log for rtems (2011-06-07)
rtems-vc at rtems.org
rtems-vc at rtems.org
Tue Jun 7 14:10:15 UTC 2011
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* configure.ac, startup/start.S: Use standard cache BSP options.
M 1.66 c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog
M 1.17 c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
M 1.8 c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.65 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.66
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog:1.65 Tue Jun 7 04:14:05 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog Tue Jun 7 08:30:45 2011
@@ -1,5 +1,9 @@
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+ * configure.ac, startup/start.S: Use standard cache BSP options.
+
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
* clock/clock-config.c: Fixes to pass psnsext01.
* startup/bspstart.c: Workaround for GCC 4.6 bug.
* include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.16 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.17
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac:1.16 Wed Feb 2 09:00:06 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac Tue Jun 7 08:30:46 2011
@@ -23,19 +23,15 @@
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[gwlcfm],[])
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[mpc5566evb],[1])
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
-[If defined, the data cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[gwlcfm],[])
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[mpc5566evb],[1])
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb],[1])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([gwlcfm],[])
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5566evb],[1])
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[])
RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS],
diff -u rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S:1.7 rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S:1.8
--- rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S:1.7 Wed Dec 29 04:54:57 2010
+++ rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S Tue Jun 7 08:30:47 2011
@@ -83,10 +83,10 @@
/* Config internal flash */
bl SYM (mpc55xx_flash_config)
-#if DATA_CACHE_ENABLE || INSTRUCTION_CACHE_ENABLE
+#if BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED
/* FIXME: Config cache */
bl config_cache
-#endif /* DATA_CACHE_ENABLE || INSTRUCTION_CACHE_ENABLE */
+#endif /* BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED */
/*
* TODO, FIXME: Enable cache in the MMU for the SRAM
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* configure.ac, startup/bspstart.c, include/coverhd.h: Use standard
cache BSP options.
M 1.176 c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
M 1.35 c/src/lib/libbsp/powerpc/mbx8xx/configure.ac
M 1.7 c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h
M 1.32 c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c
diff -u rtems/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog:1.175 rtems/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog:1.176
--- rtems/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog:1.175 Fri Feb 11 06:46:34 2011
+++ rtems/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog Tue Jun 7 08:32:31 2011
@@ -1,3 +1,8 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac, startup/bspstart.c, include/coverhd.h: Use standard
+ cache BSP options.
+
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* console/console.c, irq/irq.c:
diff -u rtems/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac:1.34 rtems/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac:1.35
--- rtems/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac:1.34 Wed Feb 2 09:00:02 2011
+++ rtems/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac Tue Jun 7 08:32:31 2011
@@ -18,22 +18,12 @@
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[mbx860_005b],[0])
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators.])
-
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
-[If defined, the data cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mbx860_005b],[])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[mbx860_005b],[0])
RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[*],[1])
diff -u rtems/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h:1.6 rtems/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h:1.7
--- rtems/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h:1.6 Fri Mar 17 04:11:37 2006
+++ rtems/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h Tue Jun 7 08:32:31 2011
@@ -32,7 +32,7 @@
#endif
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
-#if defined( INSTRUCTION_CACHE_ENABLE )
+#if BSP_INSTRUCTION_CACHE_ENABLED
/*
* 50 MHz processor, cache enabled.
*/
@@ -190,10 +190,10 @@
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
-#endif /* defined( INSTRUCTION_CACHE_ENABLE ) */
+#endif /* BSP_INSTRUCTION_CACHE_ENABLED */
#else
-#if defined( INSTRUCTION_CACHE_ENABLE )
+#if BSP_INSTRUCTION_CACHE_ENABLED
/*
* 40 MHz processor, cache enabled.
*/
@@ -351,7 +351,7 @@
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
-#endif /* defined( INSTRUCTION_CACHE_ENABLE ) */
+#endif /* BSP_INSTRUCTION_CACHE_ENABLED */
#endif
diff -u rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c:1.31 rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c:1.32
--- rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c:1.31 Sun Apr 25 17:36:25 2010
+++ rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c Tue Jun 7 08:32:31 2011
@@ -106,10 +106,10 @@
if ( nvram->cache_mode & 0x01 )
rtems_cache_enable_data();
#else
-#ifdef INSTRUCTION_CACHE_ENABLE
+#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
-#ifdef DATA_CACHE_ENABLE
+#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
#endif
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* configure.ac: Use standard cache BSP options.
M 1.20 c/src/lib/libbsp/powerpc/beatnik/ChangeLog
M 1.6 c/src/lib/libbsp/powerpc/beatnik/configure.ac
M 1.94 c/src/lib/libbsp/powerpc/ep1a/ChangeLog
M 1.17 c/src/lib/libbsp/powerpc/ep1a/configure.ac
M 1.160 c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog
M 1.38 c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac
M 1.56 c/src/lib/libbsp/powerpc/mvme3100/ChangeLog
M 1.13 c/src/lib/libbsp/powerpc/mvme3100/configure.ac
M 1.129 c/src/lib/libbsp/powerpc/mvme5500/ChangeLog
M 1.19 c/src/lib/libbsp/powerpc/mvme5500/configure.ac
diff -u rtems/c/src/lib/libbsp/powerpc/beatnik/ChangeLog:1.19 rtems/c/src/lib/libbsp/powerpc/beatnik/ChangeLog:1.20
--- rtems/c/src/lib/libbsp/powerpc/beatnik/ChangeLog:1.19 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/beatnik/ChangeLog Tue Jun 7 08:35:15 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/beatnik/configure.ac:1.5 rtems/c/src/lib/libbsp/powerpc/beatnik/configure.ac:1.6
--- rtems/c/src/lib/libbsp/powerpc/beatnik/configure.ac:1.5 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/beatnik/configure.ac Tue Jun 7 08:35:15 2011
@@ -23,14 +23,11 @@
AS=$CC
AM_PROG_AS
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
diff -u rtems/c/src/lib/libbsp/powerpc/ep1a/ChangeLog:1.93 rtems/c/src/lib/libbsp/powerpc/ep1a/ChangeLog:1.94
--- rtems/c/src/lib/libbsp/powerpc/ep1a/ChangeLog:1.93 Wed May 18 00:26:53 2011
+++ rtems/c/src/lib/libbsp/powerpc/ep1a/ChangeLog Tue Jun 7 08:35:43 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/ep1a/configure.ac:1.16 rtems/c/src/lib/libbsp/powerpc/ep1a/configure.ac:1.17
--- rtems/c/src/lib/libbsp/powerpc/ep1a/configure.ac:1.16 Wed May 18 00:26:53 2011
+++ rtems/c/src/lib/libbsp/powerpc/ep1a/configure.ac Tue Jun 7 08:35:43 2011
@@ -15,19 +15,11 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
diff -u rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog:1.159 rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog:1.160
--- rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog:1.159 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog Tue Jun 7 08:33:18 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac:1.37 rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac:1.38
--- rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac:1.37 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac Tue Jun 7 08:33:18 2011
@@ -22,14 +22,11 @@
AS=$CC
AM_PROG_AS
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
diff -u rtems/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog:1.55 rtems/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog:1.56
--- rtems/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog:1.55 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog Tue Jun 7 08:27:06 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/mvme3100/configure.ac:1.12 rtems/c/src/lib/libbsp/powerpc/mvme3100/configure.ac:1.13
--- rtems/c/src/lib/libbsp/powerpc/mvme3100/configure.ac:1.12 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/mvme3100/configure.ac Tue Jun 7 08:27:06 2011
@@ -26,14 +26,11 @@
dnl AM_CONDITIONAL([AMPOLISH3],[test x"$USE_MAINTAINER_MODE" = x"yes" \
dnl && test -n "$AMPOLISH3"])
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
diff -u rtems/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog:1.128 rtems/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog:1.129
--- rtems/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog:1.128 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog Tue Jun 7 08:26:40 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/mvme5500/configure.ac:1.18 rtems/c/src/lib/libbsp/powerpc/mvme5500/configure.ac:1.19
--- rtems/c/src/lib/libbsp/powerpc/mvme5500/configure.ac:1.18 Wed May 18 00:26:52 2011
+++ rtems/c/src/lib/libbsp/powerpc/mvme5500/configure.ac Tue Jun 7 08:26:40 2011
@@ -22,14 +22,11 @@
AS=$CC
AM_PROG_AS
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* configure.ac, startup/bspstart.c: Use standard cache BSP options.
M 1.155 c/src/lib/libbsp/powerpc/gen5200/ChangeLog
M 1.21 c/src/lib/libbsp/powerpc/gen5200/configure.ac
M 1.32 c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
M 1.104 c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
M 1.18 c/src/lib/libbsp/powerpc/gen83xx/configure.ac
M 1.32 c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c
M 1.156 c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
M 1.36 c/src/lib/libbsp/powerpc/mpc8260ads/configure.ac
M 1.27 c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c
M 1.188 c/src/lib/libbsp/powerpc/score603e/ChangeLog
M 1.39 c/src/lib/libbsp/powerpc/score603e/configure.ac
M 1.38 c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
diff -u rtems/c/src/lib/libbsp/powerpc/gen5200/ChangeLog:1.154 rtems/c/src/lib/libbsp/powerpc/gen5200/ChangeLog:1.155
--- rtems/c/src/lib/libbsp/powerpc/gen5200/ChangeLog:1.154 Fri Feb 11 06:46:30 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen5200/ChangeLog Tue Jun 7 08:38:54 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac, startup/bspstart.c: Use standard cache BSP options.
+
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* include/tm27.h:
diff -u rtems/c/src/lib/libbsp/powerpc/gen5200/configure.ac:1.20 rtems/c/src/lib/libbsp/powerpc/gen5200/configure.ac:1.21
--- rtems/c/src/lib/libbsp/powerpc/gen5200/configure.ac:1.20 Wed Feb 2 08:59:57 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen5200/configure.ac Tue Jun 7 08:38:54 2011
@@ -15,15 +15,11 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
-[If defined, the data cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([BENCHMARK_IRQ_PROCESSING],[*],[0])
RTEMS_BSPOPTS_HELP([BENCHMARK_IRQ_PROCESSING],
diff -u rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c:1.31 rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c:1.32
--- rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c:1.31 Fri Jan 28 14:29:51 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c Tue Jun 7 08:38:54 2011
@@ -149,10 +149,10 @@
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
- #if INSTRUCTION_CACHE_ENABLE
+ #if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
- #if DATA_CACHE_ENABLE
+ #if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
diff -u rtems/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog:1.103 rtems/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog:1.104
--- rtems/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog:1.103 Fri Feb 11 06:46:31 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog Tue Jun 7 08:34:29 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac, startup/bspstart.c: Use standard cache BSP options.
+
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* startup/cpuinit.c:
diff -u rtems/c/src/lib/libbsp/powerpc/gen83xx/configure.ac:1.17 rtems/c/src/lib/libbsp/powerpc/gen83xx/configure.ac:1.18
--- rtems/c/src/lib/libbsp/powerpc/gen83xx/configure.ac:1.17 Thu Feb 10 06:56:55 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen83xx/configure.ac Tue Jun 7 08:34:30 2011
@@ -15,15 +15,11 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
-[If defined, the data cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[1])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([MPC8313ERDB],[mpc8313erdb],[1])
RTEMS_BSPOPTS_HELP([MPC8313ERDB],
@@ -58,10 +54,6 @@
RTEMS_BSPOPTS_SET([HAS_UBOOT],[mpc8313erdb],[1])
RTEMS_BSPOPTS_HELP([HAS_UBOOT],[If defined, enables U-Boot support.])
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE], [If defined, then the PowerPC specific
- code in RTEMS will use data cache instructions to optimize the context switch code.])
-
RTEMS_BSPOPTS_SET([GEN83XX_ENABLE_INTERRUPT_NESTING],[*],[1])
RTEMS_BSPOPTS_HELP([GEN83XX_ENABLE_INTERRUPT_NESTING],[enable interrupt nesting])
diff -u rtems/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c:1.31 rtems/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c:1.32
--- rtems/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c:1.31 Mon Jan 24 09:32:04 2011
+++ rtems/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c Tue Jun 7 08:34:30 2011
@@ -96,11 +96,11 @@
* Enable instruction and data caches. Do not force writethrough mode.
*/
-#if INSTRUCTION_CACHE_ENABLE
+#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
-#if DATA_CACHE_ENABLE
+#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
diff -u rtems/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog:1.155 rtems/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog:1.156
--- rtems/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog:1.155 Fri Feb 11 06:48:37 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog Tue Jun 7 08:28:01 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac, startup/bspstart.c: Use standard cache BSP options.
+
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* include/tm27.h, irq/irq.c:
diff -u rtems/c/src/lib/libbsp/powerpc/mpc8260ads/configure.ac:1.35 rtems/c/src/lib/libbsp/powerpc/mpc8260ads/configure.ac:1.36
--- rtems/c/src/lib/libbsp/powerpc/mpc8260ads/configure.ac:1.35 Wed Feb 2 09:00:08 2011
+++ rtems/c/src/lib/libbsp/powerpc/mpc8260ads/configure.ac Tue Jun 7 08:28:01 2011
@@ -15,15 +15,11 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
-RTEMS_BSPOPTS_SET([DATA_CACHE_ENABLE],[*],[0])
-RTEMS_BSPOPTS_HELP([DATA_CACHE_ENABLE],
-[If defined, the data cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[0])
RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS],
diff -u rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c:1.26 rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c:1.27
--- rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c:1.26 Mon Aug 23 11:08:53 2010
+++ rtems/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c Tue Jun 7 08:28:01 2011
@@ -197,10 +197,10 @@
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
-#if INSTRUCTION_CACHE_ENABLE
+#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
-#if DATA_CACHE_ENABLE
+#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
diff -u rtems/c/src/lib/libbsp/powerpc/score603e/ChangeLog:1.187 rtems/c/src/lib/libbsp/powerpc/score603e/ChangeLog:1.188
--- rtems/c/src/lib/libbsp/powerpc/score603e/ChangeLog:1.187 Wed May 18 00:26:53 2011
+++ rtems/c/src/lib/libbsp/powerpc/score603e/ChangeLog Tue Jun 7 08:25:47 2011
@@ -1,3 +1,7 @@
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
+ * configure.ac, startup/bspstart.c: Use standard cache BSP options.
+
2011-05-17 Till Straumann <strauman at slac.stanford.edu>
PR1797/bsps
diff -u rtems/c/src/lib/libbsp/powerpc/score603e/configure.ac:1.38 rtems/c/src/lib/libbsp/powerpc/score603e/configure.ac:1.39
--- rtems/c/src/lib/libbsp/powerpc/score603e/configure.ac:1.38 Wed May 18 00:26:53 2011
+++ rtems/c/src/lib/libbsp/powerpc/score603e/configure.ac Tue Jun 7 08:25:47 2011
@@ -15,6 +15,12 @@
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
+
+RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[])
+RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
+
## FIXME: This should be a 1 out of 3 selection
## and is somehow coupled to USE_DINK (cf. include/gen2.h)
RTEMS_BSPOPTS_SET([SCORE603E_USE_SDS],[*],[0])
@@ -52,15 +58,6 @@
response time. The use of these registers can conflict with
other tools like debuggers.])
-RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
-RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
-[If defined, then the PowerPC specific code in RTEMS will use
- data cache instructions to optimize the context switch code.
- This code can conflict with debuggers or emulators. It is known
- to break the Corelis PowerPC emulator with at least some combinations
- of PowerPC 603e revisions and emulator versions.
- The BSP actually contains the call that enables this.])
-
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
[If defined then the BSP may reduce the available memory size
diff -u rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c:1.37 rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c:1.38
--- rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c:1.37 Fri Feb 11 06:47:19 2011
+++ rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c Tue Jun 7 08:25:47 2011
@@ -223,14 +223,14 @@
#endif
bsp_clicks_per_usec = 66 / 4;
- #if ( PPC_USE_DATA_CACHE )
+ #if BSP_DATA_CACHE_ENABLED
#if DEBUG
printk("bsp_start: cache_enable\n");
#endif
instruction_cache_enable ();
data_cache_enable ();
#if DEBUG
- printk("bsp_start: END PPC_USE_DATA_CACHE\n");
+ printk("bsp_start: END BSP_DATA_CACHE_ENABLED\n");
#endif
#endif
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* new-exceptions/bspsupport/ppc_exc_alignment.c: New file.
* Makefile.am: Reflect change above.
* new-exceptions/bspsupport/vectors.h: Declare
ppc_exc_alignment_handler().
M 1.387 c/src/lib/libcpu/powerpc/ChangeLog
M 1.64 c/src/lib/libcpu/powerpc/Makefile.am
A 1.1 c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c
M 1.10 c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
diff -u rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.386 rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.387
--- rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.386 Tue Jun 7 07:59:39 2011
+++ rtems/c/src/lib/libcpu/powerpc/ChangeLog Tue Jun 7 08:58:23 2011
@@ -1,5 +1,12 @@
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+ * new-exceptions/bspsupport/ppc_exc_alignment.c: New file.
+ * Makefile.am: Reflect change above.
+ * new-exceptions/bspsupport/vectors.h: Declare
+ ppc_exc_alignment_handler().
+
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
* new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of
PPC_USE_DATA_CACHE.
diff -u rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.63 rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.64
--- rtems/c/src/lib/libcpu/powerpc/Makefile.am:1.63 Tue Jun 7 03:23:44 2011
+++ rtems/c/src/lib/libcpu/powerpc/Makefile.am Tue Jun 7 08:58:23 2011
@@ -41,6 +41,7 @@
new-exceptions/bspsupport/ppc_exc_global_handler.c \
new-exceptions/bspsupport/ppc_exc_categories.c \
new-exceptions/bspsupport/ppc_exc_address.c \
+ new-exceptions/bspsupport/ppc_exc_alignment.c \
new-exceptions/bspsupport/ppc_exc_prologue.c
new_exceptions_exc_bspsupport_rel_CPPFLAGS = $(AM_CPPFLAGS)
diff -u /dev/null rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c:1.1
--- /dev/null Tue Jun 7 09:10:15 2011
+++ rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c Tue Jun 7 08:58:23 2011
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#include <rtems.h>
+#include <bsp/vectors.h>
+
+int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum)
+{
+ unsigned opcode = *(unsigned *) frame->EXC_SRR0;
+
+ /* Do we have a dcbz instruction? */
+ if ((opcode & 0xffe007ff) == 0x7c0007ec) {
+ unsigned clsz = (unsigned) rtems_cache_get_data_line_size();
+ unsigned a = (opcode >> 16) & 0x1f;
+ unsigned b = (opcode >> 11) & 0x1f;
+ unsigned *regs = &frame->GPR0;
+ unsigned *current = (unsigned *)
+ (((a == 0 ? 0 : regs [a]) + regs [b]) & (clsz - 1));
+ unsigned *end = current + clsz / 4;
+
+ while (current != end) {
+ *current = 0;
+ ++current;
+ }
+
+ frame->EXC_SRR0 += 4;
+
+ return 0;
+ } else {
+ return -1;
+ }
+}
diff -u rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h:1.9 rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h:1.10
--- rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h:1.9 Thu Feb 17 05:19:43 2011
+++ rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h Tue Jun 7 08:58:23 2011
@@ -509,6 +509,14 @@
void
ppc_exc_wrapup(BSP_Exception_frame *f);
+/**
+ * @brief Standard aligment handler.
+ *
+ * @retval 0 Performed a dcbz instruction.
+ * @retval -1 Otherwise.
+ */
+int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum);
+
/** @} */
/*
*sh*:
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
* shared/src/memcpy.c: New file.
M 1.249 c/src/lib/libbsp/powerpc/ChangeLog
A 1.1 c/src/lib/libbsp/powerpc/shared/src/memcpy.c
diff -u rtems/c/src/lib/libbsp/powerpc/ChangeLog:1.248 rtems/c/src/lib/libbsp/powerpc/ChangeLog:1.249
--- rtems/c/src/lib/libbsp/powerpc/ChangeLog:1.248 Tue Jun 7 08:02:50 2011
+++ rtems/c/src/lib/libbsp/powerpc/ChangeLog Tue Jun 7 09:09:31 2011
@@ -1,5 +1,9 @@
2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+ * shared/src/memcpy.c: New file.
+
+2011-06-07 Sebastian Huber <sebastian.huber at embedded-brains.de>
+
* shared/src/bsp-start-zero.S: Use BSP_DATA_CACHE_ENABLED instead of
DATA_CACHE_ENABLE.
diff -u /dev/null rtems/c/src/lib/libbsp/powerpc/shared/src/memcpy.c:1.1
--- /dev/null Tue Jun 7 09:10:15 2011
+++ rtems/c/src/lib/libbsp/powerpc/shared/src/memcpy.c Tue Jun 7 09:09:31 2011
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <info at embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#include <bspopts.h>
+#include <rtems/powerpc/powerpc.h>
+
+#if BSP_DATA_CACHE_ENABLED && PPC_CACHE_ALIGNMENT == 32
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#define CACHE_LINE_SIZE 32
+
+#define WORD_SIZE 4
+
+#define WORD_MASK (WORD_SIZE - 1)
+
+static bool aligned(const void *a, const void *b)
+{
+ return ((((uintptr_t) a) | ((uintptr_t) b)) & WORD_MASK) == 0;
+}
+
+void *memcpy(void *dst_ptr, const void *src_ptr, size_t n)
+{
+ uint8_t *dst = dst_ptr;
+ const uint8_t *src = src_ptr;
+
+ ppc_data_cache_block_touch(src);
+
+ if (__builtin_expect(n >= WORD_SIZE && aligned(src, dst), 1)) {
+ uint32_t *word_dst = (uint32_t *) dst - 1;
+ const uint32_t *word_src = (const uint32_t *) src - 1;
+
+ if (n >= 2 * CACHE_LINE_SIZE - WORD_SIZE) {
+ while ((uintptr_t) (word_dst + 1) % CACHE_LINE_SIZE != 0) {
+ uint32_t tmp;
+ __asm__ volatile (
+ "lwzu %[tmp], 0x4(%[src])\n"
+ "stwu %[tmp], 0x4(%[dst])\n"
+ : [src] "+b" (word_src),
+ [dst] "+b" (word_dst),
+ [tmp] "=&r" (tmp)
+ );
+ n -= WORD_SIZE;
+ }
+
+ while (n >= CACHE_LINE_SIZE) {
+ uint32_t dst_offset = 4;
+ uint32_t src_offset = 32 + 4;
+ uint32_t tmp0;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t tmp3;
+ __asm__ volatile (
+ "dcbz %[dst], %[dst_offset]\n"
+ "lwz %[tmp0], 0x04(%[src])\n"
+ "dcbt %[src], %[src_offset]\n"
+ "lwz %[tmp1], 0x08(%[src])\n"
+ "lwz %[tmp2], 0x0c(%[src])\n"
+ "lwz %[tmp3], 0x10(%[src])\n"
+ "stw %[tmp0], 0x04(%[dst])\n"
+ "stw %[tmp1], 0x08(%[dst])\n"
+ "stw %[tmp2], 0x0c(%[dst])\n"
+ "stw %[tmp3], 0x10(%[dst])\n"
+ "lwz %[tmp0], 0x14(%[src])\n"
+ "lwz %[tmp1], 0x18(%[src])\n"
+ "lwz %[tmp2], 0x1c(%[src])\n"
+ "lwzu %[tmp3], 0x20(%[src])\n"
+ "stw %[tmp0], 0x14(%[dst])\n"
+ "stw %[tmp1], 0x18(%[dst])\n"
+ "stw %[tmp2], 0x1c(%[dst])\n"
+ "stwu %[tmp3], 0x20(%[dst])\n"
+ : [src] "+b" (word_src),
+ [dst] "+b" (word_dst),
+ [tmp0] "=&r" (tmp0),
+ [tmp1] "=&r" (tmp1),
+ [tmp2] "=&r" (tmp2),
+ [tmp3] "=&r" (tmp3)
+ : [src_offset] "r" (src_offset),
+ [dst_offset] "r" (dst_offset)
+ );
+ n -= CACHE_LINE_SIZE;
+ }
+ }
+
+ while (n >= WORD_SIZE) {
+ uint32_t tmp;
+ __asm__ volatile (
+ "lwzu %[tmp], 0x4(%[src])\n"
+ "stwu %[tmp], 0x4(%[dst])\n"
+ : [src] "+b" (word_src),
+ [dst] "+b" (word_dst),
+ [tmp] "=&r" (tmp)
+ );
+ n -= WORD_SIZE;
+ }
+
+ dst = (uint8_t *) word_dst + 4;
+ src = (const uint8_t *) word_src + 4;
+ }
+
+ while (n > 0) {
+ *dst = *src;
+ ++src;
+ ++dst;
+ --n;
+ }
+
+ return dst_ptr;
+}
+
+#endif /* BSP_DATA_CACHE_ENABLED && PPC_CACHE_ALIGNMENT == 32 */
--
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