change log for rtems (2011-03-15)

[rtems-vc at rtems.org]

 *joel* (on branch rtems-4-10-branch):
2011-03-15	Till Straumann <strauman at slac.stanford.edu>

	* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
	initialized early for printk.

M  1.121  c/src/lib/libbsp/m68k/uC5282/ChangeLog
M 1.115.2.4  c/src/lib/libbsp/m68k/uC5282/ChangeLog
M   1.62  c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
M 1.59.2.2  c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

diff -u rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.120 rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.121
--- rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.120	Fri Mar  4 10:03:46 2011
+++ rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog	Tue Mar 15 16:34:44 2011
@@ -1,3 +1,8 @@
+2011-03-15	Till Straumann <strauman at slac.stanford.edu>
+
+	* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
+	initialized early for printk.
+
 2011-03-04	Till Straumann <strauman at slac.stanford.edu>
 
 	PR 1738/bsps

diff -u rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.115.2.3 rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.115.2.4
--- rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog:1.115.2.3	Fri Mar  4 10:03:53 2011
+++ rtems/c/src/lib/libbsp/m68k/uC5282/ChangeLog	Tue Mar 15 16:34:55 2011
@@ -1,3 +1,8 @@
+2011-03-15	Till Straumann <strauman at slac.stanford.edu>
+
+	* startup/bspstart.c: Fix clock code on qemu. Also ensure UART is
+	initialized early for printk.
+
 2011-03-04	Till Straumann <strauman at slac.stanford.edu>
 
 	PR 1738/bsps

diff -u rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.61 rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.62
--- rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.61	Thu Feb 17 07:25:10 2011
+++ rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c	Tue Mar 15 16:34:44 2011
@@ -244,6 +244,14 @@
   int   i;
   const char *clk_speed_str;
   uint32_t clk_speed, mfd, rfd;
+  uint8_t  byte;
+
+  /*
+   * Make sure UART TX is running - necessary for
+   * early printk to work. The firmware monitor
+   * usually enables this anyways but qemu doesn't!
+   */
+  MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED;
 
   /*
    * Set up default exception handler
@@ -334,12 +342,19 @@
 
   if ( 0 == clk_speed ) {
 	printk("Using some heuristics to determine clock speed...\n");
-	printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
-	if ( 0xf8 != MCF5282_CLOCK_SYNSR ) {
-	  printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n");
-	  bsp_sysReset(0);
+	byte = MCF5282_CLOCK_SYNSR;
+	if ( 0 == byte ) {
+		printk("SYNSR == 0; assuming QEMU at 66MHz\n");
+		BSP_pll_ref_clock = 8250000;
+		mfd = ( 0 << 8 ) | ( 2 << 12 );
+	} else {
+		if ( 0xf8 != byte ) {
+			printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte);
+			bsp_sysReset(0);
+		}
+		mfd = MCF5282_CLOCK_SYNCR;
 	}
-	mfd = MCF5282_CLOCK_SYNCR;
+	printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
 	rfd = (mfd >>  8) & 7;
 	mfd = (mfd >> 12) & 7;
 	/* Check against 'known' cases */

diff -u rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.59.2.1 rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.59.2.2
--- rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c:1.59.2.1	Thu Feb 17 07:25:24 2011
+++ rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c	Tue Mar 15 16:34:56 2011
@@ -244,6 +244,14 @@
   int   i;
   const char *clk_speed_str;
   uint32_t clk_speed, mfd, rfd;
+  uint8_t  byte;
+
+  /*
+   * Make sure UART TX is running - necessary for
+   * early printk to work. The firmware monitor
+   * usually enables this anyways but qemu doesn't!
+   */
+  MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED;
 
   /*
    * Set up default exception handler
@@ -334,12 +342,19 @@
 
   if ( 0 == clk_speed ) {
 	printk("Using some heuristics to determine clock speed...\n");
-	printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
-	if ( 0xf8 != MCF5282_CLOCK_SYNSR ) {
-	  printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n");
-	  bsp_sysReset(0);
+	byte = MCF5282_CLOCK_SYNSR;
+	if ( 0 == byte ) {
+		printk("SYNSR == 0; assuming QEMU at 66MHz\n");
+		BSP_pll_ref_clock = 8250000;
+		mfd = ( 0 << 8 ) | ( 2 << 12 );
+	} else {
+		if ( 0xf8 != byte ) {
+			printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte);
+			bsp_sysReset(0);
+		}
+		mfd = MCF5282_CLOCK_SYNCR;
 	}
-	mfd = MCF5282_CLOCK_SYNCR;
+	printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
 	rfd = (mfd >>  8) & 7;
 	mfd = (mfd >> 12) & 7;
 	/* Check against 'known' cases */



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